1 # SPDX-License-Identifier: (GPL-2.0-only OR BS 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 %YAML 1.2 2 %YAML 1.2
3 --- 3 ---
4 $id: http://devicetree.org/schemas/clock/qcom, 4 $id: http://devicetree.org/schemas/clock/qcom,dispcc-sm6350.yaml#
5 $schema: http://devicetree.org/meta-schemas/co 5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6 6
7 title: Qualcomm Display Clock & Reset Controll !! 7 title: Qualcomm Display Clock & Reset Controller Binding for SM6350
8 8
9 maintainers: 9 maintainers:
10 - Konrad Dybcio <konradybcio@kernel.org> !! 10 - Konrad Dybcio <konrad.dybcio@somainline.org>
11 11
12 description: | 12 description: |
13 Qualcomm display clock control module provid !! 13 Qualcomm display clock control module which supports the clocks, resets and
14 domains on SM6350. !! 14 power domains on SM6350.
15 15
16 See also:: include/dt-bindings/clock/qcom,di !! 16 See also dt-bindings/clock/qcom,dispcc-sm6350.h.
17 17
18 properties: 18 properties:
19 compatible: 19 compatible:
20 const: qcom,sm6350-dispcc 20 const: qcom,sm6350-dispcc
21 21
22 clocks: 22 clocks:
23 items: 23 items:
24 - description: Board XO source 24 - description: Board XO source
25 - description: GPLL0 source from GCC 25 - description: GPLL0 source from GCC
26 - description: Byte clock from DSI PHY 26 - description: Byte clock from DSI PHY
27 - description: Pixel clock from DSI PHY 27 - description: Pixel clock from DSI PHY
28 - description: Link clock from DP PHY 28 - description: Link clock from DP PHY
29 - description: VCO DIV clock from DP PHY 29 - description: VCO DIV clock from DP PHY
30 30
31 clock-names: 31 clock-names:
32 items: 32 items:
33 - const: bi_tcxo 33 - const: bi_tcxo
34 - const: gcc_disp_gpll0_clk 34 - const: gcc_disp_gpll0_clk
35 - const: dsi0_phy_pll_out_byteclk 35 - const: dsi0_phy_pll_out_byteclk
36 - const: dsi0_phy_pll_out_dsiclk 36 - const: dsi0_phy_pll_out_dsiclk
37 - const: dp_phy_pll_link_clk 37 - const: dp_phy_pll_link_clk
38 - const: dp_phy_pll_vco_div_clk 38 - const: dp_phy_pll_vco_div_clk
39 39
>> 40 '#clock-cells':
>> 41 const: 1
>> 42
>> 43 '#reset-cells':
>> 44 const: 1
>> 45
>> 46 '#power-domain-cells':
>> 47 const: 1
>> 48
>> 49 reg:
>> 50 maxItems: 1
>> 51
40 required: 52 required:
41 - compatible 53 - compatible
>> 54 - reg
42 - clocks 55 - clocks
43 - clock-names 56 - clock-names
>> 57 - '#clock-cells'
>> 58 - '#reset-cells'
44 - '#power-domain-cells' 59 - '#power-domain-cells'
45 60
46 allOf: !! 61 additionalProperties: false
47 - $ref: qcom,gcc.yaml# <<
48 <<
49 unevaluatedProperties: false <<
50 62
51 examples: 63 examples:
52 - | 64 - |
53 #include <dt-bindings/clock/qcom,gcc-sm635 65 #include <dt-bindings/clock/qcom,gcc-sm6350.h>
54 #include <dt-bindings/clock/qcom,rpmh.h> 66 #include <dt-bindings/clock/qcom,rpmh.h>
55 clock-controller@af00000 { 67 clock-controller@af00000 {
56 compatible = "qcom,sm6350-dispcc"; 68 compatible = "qcom,sm6350-dispcc";
57 reg = <0x0af00000 0x20000>; 69 reg = <0x0af00000 0x20000>;
58 clocks = <&rpmhcc RPMH_CXO_CLK>, 70 clocks = <&rpmhcc RPMH_CXO_CLK>,
59 <&gcc GCC_DISP_GPLL0_CLK>, 71 <&gcc GCC_DISP_GPLL0_CLK>,
60 <&dsi_phy 0>, 72 <&dsi_phy 0>,
61 <&dsi_phy 1>, 73 <&dsi_phy 1>,
62 <&dp_phy 0>, 74 <&dp_phy 0>,
63 <&dp_phy 1>; 75 <&dp_phy 1>;
64 clock-names = "bi_tcxo", 76 clock-names = "bi_tcxo",
65 "gcc_disp_gpll0_clk", 77 "gcc_disp_gpll0_clk",
66 "dsi0_phy_pll_out_byteclk" 78 "dsi0_phy_pll_out_byteclk",
67 "dsi0_phy_pll_out_dsiclk", 79 "dsi0_phy_pll_out_dsiclk",
68 "dp_phy_pll_link_clk", 80 "dp_phy_pll_link_clk",
69 "dp_phy_pll_vco_div_clk"; 81 "dp_phy_pll_vco_div_clk";
70 #clock-cells = <1>; 82 #clock-cells = <1>;
71 #reset-cells = <1>; 83 #reset-cells = <1>;
72 #power-domain-cells = <1>; 84 #power-domain-cells = <1>;
73 }; 85 };
74 ... 86 ...
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