1 # SPDX-License-Identifier: (GPL-2.0-only OR BS 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 %YAML 1.2 2 %YAML 1.2
3 --- 3 ---
4 $id: http://devicetree.org/schemas/clock/qcom, 4 $id: http://devicetree.org/schemas/clock/qcom,gcc-msm8953.yaml#
5 $schema: http://devicetree.org/meta-schemas/co 5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6 6
7 title: Qualcomm Global Clock & Reset Controlle 7 title: Qualcomm Global Clock & Reset Controller on MSM8953
8 8
9 maintainers: 9 maintainers:
10 - Adam Skladowski <a_skl39@protonmail.com> 10 - Adam Skladowski <a_skl39@protonmail.com>
11 - Sireesh Kodali <sireeshkodali@protonmail.co 11 - Sireesh Kodali <sireeshkodali@protonmail.com>
12 12
13 description: | 13 description: |
14 Qualcomm global clock control module provide 14 Qualcomm global clock control module provides the clocks, resets and power
15 domains on MSM8953. 15 domains on MSM8953.
16 16
17 See also: include/dt-bindings/clock/qcom,gcc 17 See also: include/dt-bindings/clock/qcom,gcc-msm8953.h
18 18
19 properties: 19 properties:
20 compatible: 20 compatible:
21 const: qcom,gcc-msm8953 21 const: qcom,gcc-msm8953
22 22
23 clocks: 23 clocks:
24 items: 24 items:
25 - description: Board XO source 25 - description: Board XO source
26 - description: Sleep clock source 26 - description: Sleep clock source
27 - description: Byte clock from DSI PHY0 27 - description: Byte clock from DSI PHY0
28 - description: Pixel clock from DSI PHY0 28 - description: Pixel clock from DSI PHY0
29 - description: Byte clock from DSI PHY1 29 - description: Byte clock from DSI PHY1
30 - description: Pixel clock from DSI PHY1 30 - description: Pixel clock from DSI PHY1
31 31
32 clock-names: 32 clock-names:
33 items: 33 items:
34 - const: xo 34 - const: xo
35 - const: sleep 35 - const: sleep
36 - const: dsi0pll 36 - const: dsi0pll
37 - const: dsi0pllbyte 37 - const: dsi0pllbyte
38 - const: dsi1pll 38 - const: dsi1pll
39 - const: dsi1pllbyte 39 - const: dsi1pllbyte
40 40
41 required: 41 required:
42 - compatible 42 - compatible
43 - clocks 43 - clocks
44 - clock-names 44 - clock-names
45 - '#power-domain-cells' 45 - '#power-domain-cells'
46 46
47 allOf: 47 allOf:
48 - $ref: qcom,gcc.yaml# 48 - $ref: qcom,gcc.yaml#
49 49
50 unevaluatedProperties: false 50 unevaluatedProperties: false
51 51
52 examples: 52 examples:
53 - | 53 - |
54 #include <dt-bindings/clock/qcom,rpmcc.h> 54 #include <dt-bindings/clock/qcom,rpmcc.h>
55 55
56 clock-controller@1800000 { 56 clock-controller@1800000 {
57 compatible = "qcom,gcc-msm8953"; 57 compatible = "qcom,gcc-msm8953";
58 reg = <0x01800000 0x80000>; 58 reg = <0x01800000 0x80000>;
59 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, 59 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
60 <&sleep_clk>, 60 <&sleep_clk>,
61 <&dsi0_phy 1>, 61 <&dsi0_phy 1>,
62 <&dsi0_phy 0>, 62 <&dsi0_phy 0>,
63 <&dsi1_phy 1>, 63 <&dsi1_phy 1>,
64 <&dsi1_phy 0>; 64 <&dsi1_phy 0>;
65 clock-names = "xo", 65 clock-names = "xo",
66 "sleep", 66 "sleep",
67 "dsi0pll", 67 "dsi0pll",
68 "dsi0pllbyte", 68 "dsi0pllbyte",
69 "dsi1pll", 69 "dsi1pll",
70 "dsi1pllbyte"; 70 "dsi1pllbyte";
71 #clock-cells = <1>; 71 #clock-cells = <1>;
72 #reset-cells = <1>; 72 #reset-cells = <1>;
73 #power-domain-cells = <1>; 73 #power-domain-cells = <1>;
74 }; 74 };
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