1 # SPDX-License-Identifier: (GPL-2.0-only OR BS 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 %YAML 1.2 2 %YAML 1.2
3 --- 3 ---
4 $id: http://devicetree.org/schemas/clock/qcom, 4 $id: http://devicetree.org/schemas/clock/qcom,gpucc.yaml#
5 $schema: http://devicetree.org/meta-schemas/co 5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6 6
7 title: Qualcomm Graphics Clock & Reset Control 7 title: Qualcomm Graphics Clock & Reset Controller
8 8
9 maintainers: 9 maintainers:
10 - Taniya Das <quic_tdas@quicinc.com> 10 - Taniya Das <quic_tdas@quicinc.com>
11 11
12 description: | 12 description: |
13 Qualcomm graphics clock control module provi 13 Qualcomm graphics clock control module provides the clocks, resets and power
14 domains on Qualcomm SoCs. 14 domains on Qualcomm SoCs.
15 15
16 See also:: 16 See also::
17 include/dt-bindings/clock/qcom,gpucc-sdm84 17 include/dt-bindings/clock/qcom,gpucc-sdm845.h
18 include/dt-bindings/clock/qcom,gpucc-sa877 18 include/dt-bindings/clock/qcom,gpucc-sa8775p.h
19 include/dt-bindings/clock/qcom,gpucc-sc718 19 include/dt-bindings/clock/qcom,gpucc-sc7180.h
20 include/dt-bindings/clock/qcom,gpucc-sc728 20 include/dt-bindings/clock/qcom,gpucc-sc7280.h
21 include/dt-bindings/clock/qcom,gpucc-sc828 21 include/dt-bindings/clock/qcom,gpucc-sc8280xp.h
22 include/dt-bindings/clock/qcom,gpucc-sm635 22 include/dt-bindings/clock/qcom,gpucc-sm6350.h
23 include/dt-bindings/clock/qcom,gpucc-sm815 23 include/dt-bindings/clock/qcom,gpucc-sm8150.h
24 include/dt-bindings/clock/qcom,gpucc-sm825 24 include/dt-bindings/clock/qcom,gpucc-sm8250.h
25 include/dt-bindings/clock/qcom,gpucc-sm835 25 include/dt-bindings/clock/qcom,gpucc-sm8350.h
26 26
27 properties: 27 properties:
28 compatible: 28 compatible:
29 enum: 29 enum:
30 - qcom,sdm845-gpucc 30 - qcom,sdm845-gpucc
31 - qcom,sa8775p-gpucc 31 - qcom,sa8775p-gpucc
32 - qcom,sc7180-gpucc 32 - qcom,sc7180-gpucc
33 - qcom,sc7280-gpucc 33 - qcom,sc7280-gpucc
34 - qcom,sc8180x-gpucc 34 - qcom,sc8180x-gpucc
35 - qcom,sc8280xp-gpucc 35 - qcom,sc8280xp-gpucc
36 - qcom,sm6350-gpucc 36 - qcom,sm6350-gpucc
37 - qcom,sm8150-gpucc 37 - qcom,sm8150-gpucc
38 - qcom,sm8250-gpucc 38 - qcom,sm8250-gpucc
39 - qcom,sm8350-gpucc 39 - qcom,sm8350-gpucc
40 40
41 clocks: 41 clocks:
42 items: 42 items:
43 - description: Board XO source 43 - description: Board XO source
44 - description: GPLL0 main branch source 44 - description: GPLL0 main branch source
45 - description: GPLL0 div branch source 45 - description: GPLL0 div branch source
46 46
47 clock-names: 47 clock-names:
48 items: 48 items:
49 - const: bi_tcxo 49 - const: bi_tcxo
50 - const: gcc_gpu_gpll0_clk_src 50 - const: gcc_gpu_gpll0_clk_src
51 - const: gcc_gpu_gpll0_div_clk_src 51 - const: gcc_gpu_gpll0_div_clk_src
52 52
53 power-domains: 53 power-domains:
54 maxItems: 1 54 maxItems: 1
55 55
56 vdd-gfx-supply: 56 vdd-gfx-supply:
57 description: Regulator supply for the VDD_ 57 description: Regulator supply for the VDD_GFX pads
58 58
>> 59 '#clock-cells':
>> 60 const: 1
>> 61
>> 62 '#reset-cells':
>> 63 const: 1
>> 64
>> 65 '#power-domain-cells':
>> 66 const: 1
>> 67
>> 68 reg:
>> 69 maxItems: 1
>> 70
59 required: 71 required:
60 - compatible 72 - compatible
>> 73 - reg
61 - clocks 74 - clocks
62 - clock-names 75 - clock-names
>> 76 - '#clock-cells'
>> 77 - '#reset-cells'
63 - '#power-domain-cells' 78 - '#power-domain-cells'
64 79
65 # Require that power-domains and vdd-gfx-suppl 80 # Require that power-domains and vdd-gfx-supply are not both present
66 not: 81 not:
67 required: 82 required:
68 - power-domains 83 - power-domains
69 - vdd-gfx-supply 84 - vdd-gfx-supply
70 85
71 allOf: !! 86 additionalProperties: false
72 - $ref: qcom,gcc.yaml# <<
73 <<
74 unevaluatedProperties: false <<
75 87
76 examples: 88 examples:
77 - | 89 - |
78 #include <dt-bindings/clock/qcom,gcc-sdm84 90 #include <dt-bindings/clock/qcom,gcc-sdm845.h>
79 #include <dt-bindings/clock/qcom,rpmh.h> 91 #include <dt-bindings/clock/qcom,rpmh.h>
80 clock-controller@5090000 { 92 clock-controller@5090000 {
81 compatible = "qcom,sdm845-gpucc"; 93 compatible = "qcom,sdm845-gpucc";
82 reg = <0x05090000 0x9000>; 94 reg = <0x05090000 0x9000>;
83 clocks = <&rpmhcc RPMH_CXO_CLK>, 95 clocks = <&rpmhcc RPMH_CXO_CLK>,
84 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 96 <&gcc GCC_GPU_GPLL0_CLK_SRC>,
85 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC 97 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
86 clock-names = "bi_tcxo", 98 clock-names = "bi_tcxo",
87 "gcc_gpu_gpll0_clk_src", 99 "gcc_gpu_gpll0_clk_src",
88 "gcc_gpu_gpll0_div_clk_src 100 "gcc_gpu_gpll0_div_clk_src";
89 #clock-cells = <1>; 101 #clock-cells = <1>;
90 #reset-cells = <1>; 102 #reset-cells = <1>;
91 #power-domain-cells = <1>; 103 #power-domain-cells = <1>;
92 }; 104 };
93 ... 105 ...
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