1 # SPDX-License-Identifier: (GPL-2.0-only OR BS 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 %YAML 1.2 2 %YAML 1.2
3 --- 3 ---
4 $id: http://devicetree.org/schemas/clock/qcom, 4 $id: http://devicetree.org/schemas/clock/qcom,ipq5332-gcc.yaml#
5 $schema: http://devicetree.org/meta-schemas/co 5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6 6
7 title: Qualcomm Global Clock & Reset Controlle 7 title: Qualcomm Global Clock & Reset Controller on IPQ5332
8 8
9 maintainers: 9 maintainers:
10 - Bjorn Andersson <andersson@kernel.org> 10 - Bjorn Andersson <andersson@kernel.org>
11 11
12 description: | 12 description: |
13 Qualcomm global clock control module provide 13 Qualcomm global clock control module provides the clocks, resets and power
14 domains on IPQ5332. 14 domains on IPQ5332.
15 15
16 See also:: include/dt-bindings/clock/qcom,gc 16 See also:: include/dt-bindings/clock/qcom,gcc-ipq5332.h
17 17
18 allOf: 18 allOf:
19 - $ref: qcom,gcc.yaml# 19 - $ref: qcom,gcc.yaml#
20 20
21 properties: 21 properties:
22 compatible: 22 compatible:
23 const: qcom,ipq5332-gcc 23 const: qcom,ipq5332-gcc
24 24
25 clocks: 25 clocks:
26 items: 26 items:
27 - description: Board XO clock source 27 - description: Board XO clock source
28 - description: Sleep clock source 28 - description: Sleep clock source
29 - description: PCIE 2lane PHY pipe clock 29 - description: PCIE 2lane PHY pipe clock source
30 - description: PCIE 2lane x1 PHY pipe cl 30 - description: PCIE 2lane x1 PHY pipe clock source (For second lane)
31 - description: USB PCIE wrapper pipe clo 31 - description: USB PCIE wrapper pipe clock source
32 32
33 '#power-domain-cells': false <<
34 '#interconnect-cells': <<
35 const: 1 <<
36 <<
37 required: 33 required:
38 - compatible 34 - compatible
39 - clocks 35 - clocks
40 36
41 unevaluatedProperties: false 37 unevaluatedProperties: false
42 38
43 examples: 39 examples:
44 - | 40 - |
45 clock-controller@1800000 { 41 clock-controller@1800000 {
46 compatible = "qcom,ipq5332-gcc"; 42 compatible = "qcom,ipq5332-gcc";
47 reg = <0x01800000 0x80000>; 43 reg = <0x01800000 0x80000>;
48 clocks = <&xo_board>, 44 clocks = <&xo_board>,
49 <&sleep_clk>, 45 <&sleep_clk>,
50 <&pcie_2lane_phy_pipe_clk>, 46 <&pcie_2lane_phy_pipe_clk>,
51 <&pcie_2lane_phy_pipe_clk_x1>, 47 <&pcie_2lane_phy_pipe_clk_x1>,
52 <&usb_pcie_wrapper_pipe_clk>; 48 <&usb_pcie_wrapper_pipe_clk>;
53 #clock-cells = <1>; 49 #clock-cells = <1>;
>> 50 #power-domain-cells = <1>;
54 #reset-cells = <1>; 51 #reset-cells = <1>;
55 }; 52 };
56 ... 53 ...
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