1 # SPDX-License-Identifier: (GPL-2.0-only OR BS 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 %YAML 1.2 2 %YAML 1.2
3 --- 3 ---
4 $id: http://devicetree.org/schemas/clock/qcom, 4 $id: http://devicetree.org/schemas/clock/qcom,sm4450-dispcc.yaml#
5 $schema: http://devicetree.org/meta-schemas/co 5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6 6
7 title: Qualcomm Display Clock & Reset Controll 7 title: Qualcomm Display Clock & Reset Controller on SM4450
8 8
9 maintainers: 9 maintainers:
10 - Ajit Pandey <quic_ajipan@quicinc.com> 10 - Ajit Pandey <quic_ajipan@quicinc.com>
11 - Taniya Das <quic_tdas@quicinc.com> 11 - Taniya Das <quic_tdas@quicinc.com>
12 12
13 description: | 13 description: |
14 Qualcomm display clock control module provid 14 Qualcomm display clock control module provides the clocks, resets and power
15 domains on SM4450 15 domains on SM4450
16 16
17 See also:: include/dt-bindings/clock/qcom,sm 17 See also:: include/dt-bindings/clock/qcom,sm4450-dispcc.h
18 18
19 properties: 19 properties:
20 compatible: 20 compatible:
21 const: qcom,sm4450-dispcc 21 const: qcom,sm4450-dispcc
22 22
23 reg: 23 reg:
24 maxItems: 1 24 maxItems: 1
25 25
26 clocks: 26 clocks:
27 items: 27 items:
28 - description: Board XO source 28 - description: Board XO source
29 - description: Board active XO source 29 - description: Board active XO source
30 - description: Display AHB clock source 30 - description: Display AHB clock source from GCC
31 - description: sleep clock source 31 - description: sleep clock source
32 - description: Byte clock from DSI PHY0 32 - description: Byte clock from DSI PHY0
33 - description: Pixel clock from DSI PHY0 33 - description: Pixel clock from DSI PHY0
34 34
35 '#clock-cells': 35 '#clock-cells':
36 const: 1 36 const: 1
37 37
38 '#reset-cells': 38 '#reset-cells':
39 const: 1 39 const: 1
40 40
41 '#power-domain-cells': 41 '#power-domain-cells':
42 const: 1 42 const: 1
43 43
44 required: 44 required:
45 - compatible 45 - compatible
46 - reg 46 - reg
47 - clocks 47 - clocks
48 - '#clock-cells' 48 - '#clock-cells'
49 - '#reset-cells' 49 - '#reset-cells'
50 - '#power-domain-cells' 50 - '#power-domain-cells'
51 51
52 additionalProperties: false 52 additionalProperties: false
53 53
54 examples: 54 examples:
55 - | 55 - |
56 #include <dt-bindings/clock/qcom,rpmh.h> 56 #include <dt-bindings/clock/qcom,rpmh.h>
57 #include <dt-bindings/clock/qcom,sm4450-gc 57 #include <dt-bindings/clock/qcom,sm4450-gcc.h>
58 clock-controller@af00000 { 58 clock-controller@af00000 {
59 compatible = "qcom,sm4450-dispcc"; 59 compatible = "qcom,sm4450-dispcc";
60 reg = <0x0af00000 0x20000>; 60 reg = <0x0af00000 0x20000>;
61 clocks = <&rpmhcc RPMH_CXO_CLK>, 61 clocks = <&rpmhcc RPMH_CXO_CLK>,
62 <&rpmhcc RPMH_CXO_CLK_A>, 62 <&rpmhcc RPMH_CXO_CLK_A>,
63 <&gcc GCC_DISP_AHB_CLK>, 63 <&gcc GCC_DISP_AHB_CLK>,
64 <&sleep_clk>, 64 <&sleep_clk>,
65 <&dsi0_phy_pll_out_byteclk>, 65 <&dsi0_phy_pll_out_byteclk>,
66 <&dsi0_phy_pll_out_dsiclk>; 66 <&dsi0_phy_pll_out_dsiclk>;
67 #clock-cells = <1>; 67 #clock-cells = <1>;
68 #reset-cells = <1>; 68 #reset-cells = <1>;
69 #power-domain-cells = <1>; 69 #power-domain-cells = <1>;
70 }; 70 };
71 ... 71 ...
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