1 # SPDX-License-Identifier: (GPL-2.0-only OR BS 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 %YAML 1.2 2 %YAML 1.2
3 --- 3 ---
4 $id: http://devicetree.org/schemas/clock/qcom, 4 $id: http://devicetree.org/schemas/clock/qcom,sm8450-gpucc.yaml#
5 $schema: http://devicetree.org/meta-schemas/co 5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6 6
7 title: Qualcomm Graphics Clock & Reset Control 7 title: Qualcomm Graphics Clock & Reset Controller on SM8450
8 8
9 maintainers: 9 maintainers:
10 - Konrad Dybcio <konradybcio@kernel.org> 10 - Konrad Dybcio <konradybcio@kernel.org>
11 11
12 description: | 12 description: |
13 Qualcomm graphics clock control module provi 13 Qualcomm graphics clock control module provides the clocks, resets and power
14 domains on Qualcomm SoCs. 14 domains on Qualcomm SoCs.
15 15
16 See also:: 16 See also::
17 include/dt-bindings/clock/qcom,sm4450-gpuc 17 include/dt-bindings/clock/qcom,sm4450-gpucc.h
18 include/dt-bindings/clock/qcom,sm8450-gpuc 18 include/dt-bindings/clock/qcom,sm8450-gpucc.h
19 include/dt-bindings/clock/qcom,sm8550-gpuc 19 include/dt-bindings/clock/qcom,sm8550-gpucc.h
20 include/dt-bindings/reset/qcom,sm8450-gpuc 20 include/dt-bindings/reset/qcom,sm8450-gpucc.h
21 include/dt-bindings/reset/qcom,sm8650-gpuc 21 include/dt-bindings/reset/qcom,sm8650-gpucc.h
22 include/dt-bindings/reset/qcom,x1e80100-gp 22 include/dt-bindings/reset/qcom,x1e80100-gpucc.h
23 23
24 properties: 24 properties:
25 compatible: 25 compatible:
26 enum: 26 enum:
27 - qcom,sm4450-gpucc 27 - qcom,sm4450-gpucc
28 - qcom,sm8450-gpucc 28 - qcom,sm8450-gpucc
29 - qcom,sm8550-gpucc 29 - qcom,sm8550-gpucc
30 - qcom,sm8650-gpucc 30 - qcom,sm8650-gpucc
31 - qcom,x1e80100-gpucc 31 - qcom,x1e80100-gpucc
32 32
33 clocks: 33 clocks:
34 items: 34 items:
35 - description: Board XO source 35 - description: Board XO source
36 - description: GPLL0 main branch source 36 - description: GPLL0 main branch source
37 - description: GPLL0 div branch source 37 - description: GPLL0 div branch source
38 38
39 required: 39 required:
40 - compatible 40 - compatible
41 - clocks 41 - clocks
42 - '#power-domain-cells' 42 - '#power-domain-cells'
43 43
44 allOf: 44 allOf:
45 - $ref: qcom,gcc.yaml# 45 - $ref: qcom,gcc.yaml#
46 46
47 unevaluatedProperties: false 47 unevaluatedProperties: false
48 48
49 examples: 49 examples:
50 - | 50 - |
51 #include <dt-bindings/clock/qcom,gcc-sm845 51 #include <dt-bindings/clock/qcom,gcc-sm8450.h>
52 #include <dt-bindings/clock/qcom,rpmh.h> 52 #include <dt-bindings/clock/qcom,rpmh.h>
53 53
54 soc { 54 soc {
55 #address-cells = <2>; 55 #address-cells = <2>;
56 #size-cells = <2>; 56 #size-cells = <2>;
57 57
58 clock-controller@3d90000 { 58 clock-controller@3d90000 {
59 compatible = "qcom,sm8450-gpucc"; 59 compatible = "qcom,sm8450-gpucc";
60 reg = <0 0x03d90000 0 0xa000>; 60 reg = <0 0x03d90000 0 0xa000>;
61 clocks = <&rpmhcc RPMH_CXO_CLK>, 61 clocks = <&rpmhcc RPMH_CXO_CLK>,
62 <&gcc GCC_GPU_GPLL0_CLK_S 62 <&gcc GCC_GPU_GPLL0_CLK_SRC>,
63 <&gcc GCC_GPU_GPLL0_DIV_C 63 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
64 #clock-cells = <1>; 64 #clock-cells = <1>;
65 #reset-cells = <1>; 65 #reset-cells = <1>;
66 #power-domain-cells = <1>; 66 #power-domain-cells = <1>;
67 }; 67 };
68 }; 68 };
69 ... 69 ...
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