1 # SPDX-License-Identifier: (GPL-2.0-only OR BS 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 %YAML 1.2 2 %YAML 1.2
3 --- 3 ---
4 $id: http://devicetree.org/schemas/clock/qcom, 4 $id: http://devicetree.org/schemas/clock/qcom,x1e80100-gcc.yaml#
5 $schema: http://devicetree.org/meta-schemas/co 5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6 6
7 title: Qualcomm Global Clock & Reset Controlle 7 title: Qualcomm Global Clock & Reset Controller on X1E80100
8 8
9 maintainers: 9 maintainers:
10 - Rajendra Nayak <quic_rjendra@quicinc.com> 10 - Rajendra Nayak <quic_rjendra@quicinc.com>
11 11
12 description: | 12 description: |
13 Qualcomm global clock control module provide 13 Qualcomm global clock control module provides the clocks, resets and power
14 domains on X1E80100 14 domains on X1E80100
15 15
16 See also:: include/dt-bindings/clock/qcom,x1 16 See also:: include/dt-bindings/clock/qcom,x1e80100-gcc.h
17 17
18 properties: 18 properties:
19 compatible: 19 compatible:
20 const: qcom,x1e80100-gcc 20 const: qcom,x1e80100-gcc
21 21
22 clocks: 22 clocks:
23 items: 23 items:
24 - description: Board XO source 24 - description: Board XO source
25 - description: Sleep clock source 25 - description: Sleep clock source
26 - description: PCIe 3 pipe clock 26 - description: PCIe 3 pipe clock
27 - description: PCIe 4 pipe clock 27 - description: PCIe 4 pipe clock
28 - description: PCIe 5 pipe clock 28 - description: PCIe 5 pipe clock
29 - description: PCIe 6a pipe clock 29 - description: PCIe 6a pipe clock
30 - description: PCIe 6b pipe clock 30 - description: PCIe 6b pipe clock
31 - description: USB QMP Phy 0 clock sourc 31 - description: USB QMP Phy 0 clock source
32 - description: USB QMP Phy 1 clock sourc 32 - description: USB QMP Phy 1 clock source
33 - description: USB QMP Phy 2 clock sourc 33 - description: USB QMP Phy 2 clock source
34 34
35 power-domains: 35 power-domains:
36 description: 36 description:
37 A phandle and PM domain specifier for th 37 A phandle and PM domain specifier for the CX power domain.
38 maxItems: 1 38 maxItems: 1
39 39
40 required: 40 required:
41 - compatible 41 - compatible
42 - clocks 42 - clocks
43 - power-domains 43 - power-domains
44 - '#power-domain-cells' 44 - '#power-domain-cells'
45 45
46 allOf: 46 allOf:
47 - $ref: qcom,gcc.yaml# 47 - $ref: qcom,gcc.yaml#
48 48
49 unevaluatedProperties: false 49 unevaluatedProperties: false
50 50
51 examples: 51 examples:
52 - | 52 - |
53 #include <dt-bindings/power/qcom,rpmhpd.h> 53 #include <dt-bindings/power/qcom,rpmhpd.h>
54 clock-controller@100000 { 54 clock-controller@100000 {
55 compatible = "qcom,x1e80100-gcc"; 55 compatible = "qcom,x1e80100-gcc";
56 reg = <0x00100000 0x200000>; 56 reg = <0x00100000 0x200000>;
57 clocks = <&bi_tcxo_div2>, 57 clocks = <&bi_tcxo_div2>,
58 <&sleep_clk>, 58 <&sleep_clk>,
59 <&pcie3_phy>, 59 <&pcie3_phy>,
60 <&pcie4_phy>, 60 <&pcie4_phy>,
61 <&pcie5_phy>, 61 <&pcie5_phy>,
62 <&pcie6a_phy>, 62 <&pcie6a_phy>,
63 <&pcie6b_phy>, 63 <&pcie6b_phy>,
64 <&usb_1_ss0_qmpphy 0>, 64 <&usb_1_ss0_qmpphy 0>,
65 <&usb_1_ss1_qmpphy 1>, 65 <&usb_1_ss1_qmpphy 1>,
66 <&usb_1_ss2_qmpphy 2>; 66 <&usb_1_ss2_qmpphy 2>;
67 power-domains = <&rpmhpd RPMHPD_CX>; 67 power-domains = <&rpmhpd RPMHPD_CX>;
68 #clock-cells = <1>; 68 #clock-cells = <1>;
69 #reset-cells = <1>; 69 #reset-cells = <1>;
70 #power-domain-cells = <1>; 70 #power-domain-cells = <1>;
71 }; 71 };
72 72
73 ... 73 ...
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