1 # SPDX-License-Identifier: (GPL-2.0-only OR BS
2 %YAML 1.2
3 ---
4 $id: http://devicetree.org/schemas/clock/renes
5 $schema: http://devicetree.org/meta-schemas/co
6
7 title: Renesas RZ/V2H(P) Clock Pulse Generator
8
9 maintainers:
10 - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.
11
12 description:
13 On Renesas RZ/V2H(P) SoCs, the CPG (Clock Pu
14 and control of clock signals for the IP modu
15 and control over booting, low power consumpt
16
17 properties:
18 compatible:
19 const: renesas,r9a09g057-cpg
20
21 reg:
22 maxItems: 1
23
24 clocks:
25 items:
26 - description: AUDIO_EXTAL clock input
27 - description: RTXIN clock input
28 - description: QEXTAL clock input
29
30 clock-names:
31 items:
32 - const: audio_extal
33 - const: rtxin
34 - const: qextal
35
36 '#clock-cells':
37 description: |
38 - For CPG core clocks, the two clock spe
39 and a core clock reference, as defined
40 <dt-bindings/clock/renesas,r9a09g057-c
41 - For module clocks, the two clock speci
42 a module number. The module number is
43 offset index multiplied by 16, plus th
44 used to turn the CLK ON. For example,
45 calculation is (1 * 16 + 3) = 0x13.
46 const: 2
47
48 '#power-domain-cells':
49 const: 0
50
51 '#reset-cells':
52 description:
53 The single reset specifier cell must be
54 is calculated as the reset register offs
55 actual bit in the register used to reset
56 for SYS_0_PRESETN, the calculation is (3
57 const: 1
58
59 required:
60 - compatible
61 - reg
62 - clocks
63 - clock-names
64 - '#clock-cells'
65 - '#power-domain-cells'
66 - '#reset-cells'
67
68 additionalProperties: false
69
70 examples:
71 - |
72 clock-controller@10420000 {
73 compatible = "renesas,r9a09g057-cpg";
74 reg = <0x10420000 0x10000>;
75 clocks = <&audio_extal_clk>, <&rtxin_c
76 clock-names = "audio_extal", "rtxin",
77 #clock-cells = <2>;
78 #power-domain-cells = <0>;
79 #reset-cells = <1>;
80 };
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