1 # SPDX-License-Identifier: (GPL-2.0-only OR BS 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 %YAML 1.2 2 %YAML 1.2
3 --- 3 ---
4 $id: http://devicetree.org/schemas/clock/renes 4 $id: http://devicetree.org/schemas/clock/renesas,rzv2h-cpg.yaml#
5 $schema: http://devicetree.org/meta-schemas/co 5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6 6
7 title: Renesas RZ/V2H(P) Clock Pulse Generator 7 title: Renesas RZ/V2H(P) Clock Pulse Generator (CPG)
8 8
9 maintainers: 9 maintainers:
10 - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp. 10 - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
11 11
12 description: 12 description:
13 On Renesas RZ/V2H(P) SoCs, the CPG (Clock Pu 13 On Renesas RZ/V2H(P) SoCs, the CPG (Clock Pulse Generator) handles generation
14 and control of clock signals for the IP modu 14 and control of clock signals for the IP modules, generation and control of resets,
15 and control over booting, low power consumpt 15 and control over booting, low power consumption and power supply domains.
16 16
17 properties: 17 properties:
18 compatible: 18 compatible:
19 const: renesas,r9a09g057-cpg 19 const: renesas,r9a09g057-cpg
20 20
21 reg: 21 reg:
22 maxItems: 1 22 maxItems: 1
23 23
24 clocks: 24 clocks:
25 items: 25 items:
26 - description: AUDIO_EXTAL clock input 26 - description: AUDIO_EXTAL clock input
27 - description: RTXIN clock input 27 - description: RTXIN clock input
28 - description: QEXTAL clock input 28 - description: QEXTAL clock input
29 29
30 clock-names: 30 clock-names:
31 items: 31 items:
32 - const: audio_extal 32 - const: audio_extal
33 - const: rtxin 33 - const: rtxin
34 - const: qextal 34 - const: qextal
35 35
36 '#clock-cells': 36 '#clock-cells':
37 description: | 37 description: |
38 - For CPG core clocks, the two clock spe 38 - For CPG core clocks, the two clock specifier cells must be "CPG_CORE"
39 and a core clock reference, as defined 39 and a core clock reference, as defined in
40 <dt-bindings/clock/renesas,r9a09g057-c 40 <dt-bindings/clock/renesas,r9a09g057-cpg.h>,
41 - For module clocks, the two clock speci 41 - For module clocks, the two clock specifier cells must be "CPG_MOD" and
42 a module number. The module number is 42 a module number. The module number is calculated as the CLKON register
43 offset index multiplied by 16, plus th 43 offset index multiplied by 16, plus the actual bit in the register
44 used to turn the CLK ON. For example, 44 used to turn the CLK ON. For example, for CGC_GIC_0_GICCLK, the
45 calculation is (1 * 16 + 3) = 0x13. 45 calculation is (1 * 16 + 3) = 0x13.
46 const: 2 46 const: 2
47 47
48 '#power-domain-cells': 48 '#power-domain-cells':
49 const: 0 49 const: 0
50 50
51 '#reset-cells': 51 '#reset-cells':
52 description: 52 description:
53 The single reset specifier cell must be 53 The single reset specifier cell must be the reset number. The reset number
54 is calculated as the reset register offs 54 is calculated as the reset register offset index multiplied by 16, plus the
55 actual bit in the register used to reset 55 actual bit in the register used to reset the specific IP block. For example,
56 for SYS_0_PRESETN, the calculation is (3 56 for SYS_0_PRESETN, the calculation is (3 * 16 + 0) = 0x30.
57 const: 1 57 const: 1
58 58
59 required: 59 required:
60 - compatible 60 - compatible
61 - reg 61 - reg
62 - clocks 62 - clocks
63 - clock-names 63 - clock-names
64 - '#clock-cells' 64 - '#clock-cells'
65 - '#power-domain-cells' 65 - '#power-domain-cells'
66 - '#reset-cells' 66 - '#reset-cells'
67 67
68 additionalProperties: false 68 additionalProperties: false
69 69
70 examples: 70 examples:
71 - | 71 - |
72 clock-controller@10420000 { 72 clock-controller@10420000 {
73 compatible = "renesas,r9a09g057-cpg"; 73 compatible = "renesas,r9a09g057-cpg";
74 reg = <0x10420000 0x10000>; 74 reg = <0x10420000 0x10000>;
75 clocks = <&audio_extal_clk>, <&rtxin_c 75 clocks = <&audio_extal_clk>, <&rtxin_clk>, <&qextal_clk>;
76 clock-names = "audio_extal", "rtxin", 76 clock-names = "audio_extal", "rtxin", "qextal";
77 #clock-cells = <2>; 77 #clock-cells = <2>;
78 #power-domain-cells = <0>; 78 #power-domain-cells = <0>;
79 #reset-cells = <1>; 79 #reset-cells = <1>;
80 }; 80 };
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