1 # SPDX-License-Identifier: (GPL-2.0+ OR MIT) 1 # SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 %YAML 1.2 2 %YAML 1.2
3 --- 3 ---
4 $id: http://devicetree.org/schemas/clock/rockc 4 $id: http://devicetree.org/schemas/clock/rockchip,rk3308-cru.yaml#
5 $schema: http://devicetree.org/meta-schemas/co 5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6 6
7 title: Rockchip RK3308 Clock and Reset Unit (C 7 title: Rockchip RK3308 Clock and Reset Unit (CRU)
8 8
9 maintainers: 9 maintainers:
10 - Elaine Zhang <zhangqing@rock-chips.com> 10 - Elaine Zhang <zhangqing@rock-chips.com>
11 - Heiko Stuebner <heiko@sntech.de> 11 - Heiko Stuebner <heiko@sntech.de>
12 12
13 description: | 13 description: |
14 The RK3308 clock controller generates and su 14 The RK3308 clock controller generates and supplies clocks to various
15 controllers within the SoC and also implemen 15 controllers within the SoC and also implements a reset controller for SoC
16 peripherals. 16 peripherals.
17 Each clock is assigned an identifier and cli 17 Each clock is assigned an identifier and client nodes can use this identifier
18 to specify the clock which they consume. All 18 to specify the clock which they consume. All available clocks are defined as
19 preprocessor macros in the dt-bindings/clock 19 preprocessor macros in the dt-bindings/clock/rk3308-cru.h headers and can be
20 used in device tree sources. Similar macros 20 used in device tree sources. Similar macros exist for the reset sources in
21 these files. 21 these files.
22 There are several clocks that are generated 22 There are several clocks that are generated outside the SoC. It is expected
23 that they are defined using standard clock b 23 that they are defined using standard clock bindings with following
24 clock-output-names: 24 clock-output-names:
25 - "xin24m" - 25 - "xin24m" - crystal input - required
26 - "xin32k" - 26 - "xin32k" - rtc clock - optional
27 - "mclk_i2s0_8ch_in", "mclk_i2s1_8ch_in", 27 - "mclk_i2s0_8ch_in", "mclk_i2s1_8ch_in",
28 "mclk_i2s2_8ch_in", "mclk_i2s3_8ch_in", 28 "mclk_i2s2_8ch_in", "mclk_i2s3_8ch_in",
29 "mclk_i2s0_2ch_in", "mclk_i2s1_2ch_in" - 29 "mclk_i2s0_2ch_in", "mclk_i2s1_2ch_in" - external I2S or
30 30 SPDIF clock - optional
31 - "mac_clkin" - 31 - "mac_clkin" - external MAC clock - optional
32 32
33 properties: 33 properties:
34 compatible: 34 compatible:
35 enum: 35 enum:
36 - rockchip,rk3308-cru 36 - rockchip,rk3308-cru
37 37
38 reg: 38 reg:
39 maxItems: 1 39 maxItems: 1
40 40
41 "#clock-cells": 41 "#clock-cells":
42 const: 1 42 const: 1
43 43
44 "#reset-cells": 44 "#reset-cells":
45 const: 1 45 const: 1
46 46
47 clocks: 47 clocks:
48 maxItems: 1 48 maxItems: 1
49 49
50 clock-names: 50 clock-names:
51 const: xin24m 51 const: xin24m
52 52
53 rockchip,grf: 53 rockchip,grf:
54 $ref: /schemas/types.yaml#/definitions/pha 54 $ref: /schemas/types.yaml#/definitions/phandle
55 description: 55 description:
56 Phandle to the syscon managing the "gene 56 Phandle to the syscon managing the "general register files" (GRF),
57 if missing pll rates are not changeable, 57 if missing pll rates are not changeable, due to the missing pll
58 lock status. 58 lock status.
59 59
60 required: 60 required:
61 - compatible 61 - compatible
62 - reg 62 - reg
63 - "#clock-cells" 63 - "#clock-cells"
64 - "#reset-cells" 64 - "#reset-cells"
65 65
66 additionalProperties: false 66 additionalProperties: false
67 67
68 examples: 68 examples:
69 - | 69 - |
70 cru: clock-controller@ff500000 { 70 cru: clock-controller@ff500000 {
71 compatible = "rockchip,rk3308-cru"; 71 compatible = "rockchip,rk3308-cru";
72 reg = <0xff500000 0x1000>; 72 reg = <0xff500000 0x1000>;
73 rockchip,grf = <&grf>; 73 rockchip,grf = <&grf>;
74 #clock-cells = <1>; 74 #clock-cells = <1>;
75 #reset-cells = <1>; 75 #reset-cells = <1>;
76 }; 76 };
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