1 # SPDX-License-Identifier: (GPL-2.0+ OR MIT) !! 1 # SPDX-License-Identifier: GPL-2.0-only
2 %YAML 1.2 2 %YAML 1.2
3 --- 3 ---
4 $id: http://devicetree.org/schemas/clock/rockc 4 $id: http://devicetree.org/schemas/clock/rockchip,rk3399-cru.yaml#
5 $schema: http://devicetree.org/meta-schemas/co 5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6 6
7 title: Rockchip RK3399 Clock and Reset Unit 7 title: Rockchip RK3399 Clock and Reset Unit
8 8
9 maintainers: 9 maintainers:
10 - Elaine Zhang <zhangqing@rock-chips.com> !! 10 - Xing Zheng <zhengxing@rock-chips.com>
11 - Heiko Stuebner <heiko@sntech.de> 11 - Heiko Stuebner <heiko@sntech.de>
12 12
13 description: | 13 description: |
14 The RK3399 clock controller generates and su 14 The RK3399 clock controller generates and supplies clock to various
15 controllers within the SoC and also implemen 15 controllers within the SoC and also implements a reset controller for SoC
16 peripherals. 16 peripherals.
17 Each clock is assigned an identifier and cli 17 Each clock is assigned an identifier and client nodes can use this identifier
18 to specify the clock which they consume. All 18 to specify the clock which they consume. All available clocks are defined as
19 preprocessor macros in the dt-bindings/clock 19 preprocessor macros in the dt-bindings/clock/rk3399-cru.h headers and can be
20 used in device tree sources. Similar macros 20 used in device tree sources. Similar macros exist for the reset sources in
21 these files. 21 these files.
22 There are several clocks that are generated 22 There are several clocks that are generated outside the SoC. It is expected
23 that they are defined using standard clock b 23 that they are defined using standard clock bindings with following
24 clock-output-names: 24 clock-output-names:
25 - "xin24m" - crystal input !! 25 - "xin24m" - crystal input - required,
26 - "xin32k" - rtc clock !! 26 - "xin32k" - rtc clock - optional,
27 - "clkin_gmac" - external GMAC clock !! 27 - "clkin_gmac" - external GMAC clock - optional,
28 - "clkin_i2s" - external I2S clock !! 28 - "clkin_i2s" - external I2S clock - optional,
29 - "pclkin_cif" - external ISP clock !! 29 - "pclkin_cif" - external ISP clock - optional,
30 - "clk_usbphy0_480m" - output clock of the 30 - "clk_usbphy0_480m" - output clock of the pll in the usbphy0
31 - "clk_usbphy1_480m" - output clock of the 31 - "clk_usbphy1_480m" - output clock of the pll in the usbphy1
32 32
33 properties: 33 properties:
34 compatible: 34 compatible:
35 enum: 35 enum:
36 - rockchip,rk3399-pmucru 36 - rockchip,rk3399-pmucru
37 - rockchip,rk3399-cru 37 - rockchip,rk3399-cru
38 38
39 reg: 39 reg:
40 maxItems: 1 40 maxItems: 1
41 41
42 "#clock-cells": 42 "#clock-cells":
43 const: 1 43 const: 1
44 44
45 "#reset-cells": 45 "#reset-cells":
46 const: 1 46 const: 1
47 47
48 clocks: 48 clocks:
49 maxItems: 1 !! 49 minItems: 1
50 50
51 clock-names: !! 51 assigned-clocks:
52 const: xin24m !! 52 minItems: 1
>> 53 maxItems: 64
>> 54
>> 55 assigned-clock-parents:
>> 56 minItems: 1
>> 57 maxItems: 64
>> 58
>> 59 assigned-clock-rates:
>> 60 minItems: 1
>> 61 maxItems: 64
53 62
54 rockchip,grf: 63 rockchip,grf:
55 $ref: /schemas/types.yaml#/definitions/pha 64 $ref: /schemas/types.yaml#/definitions/phandle
56 description: !! 65 description: >
57 Phandle to the syscon managing the "gene !! 66 phandle to the syscon managing the "general register files". It is used
58 for GRF muxes, if missing any muxes pres 67 for GRF muxes, if missing any muxes present in the GRF will not be
59 available. 68 available.
60 69
61 required: 70 required:
62 - compatible 71 - compatible
63 - reg 72 - reg
64 - "#clock-cells" 73 - "#clock-cells"
65 - "#reset-cells" 74 - "#reset-cells"
66 75
67 additionalProperties: false 76 additionalProperties: false
68 77
69 examples: 78 examples:
70 - | 79 - |
71 pmucru: clock-controller@ff750000 { !! 80 pmucru: pmu-clock-controller@ff750000 {
72 compatible = "rockchip,rk3399-pmucru"; 81 compatible = "rockchip,rk3399-pmucru";
73 reg = <0xff750000 0x1000>; 82 reg = <0xff750000 0x1000>;
74 #clock-cells = <1>; 83 #clock-cells = <1>;
75 #reset-cells = <1>; 84 #reset-cells = <1>;
76 }; 85 };
77 - | 86 - |
78 cru: clock-controller@ff760000 { 87 cru: clock-controller@ff760000 {
79 compatible = "rockchip,rk3399-cru"; 88 compatible = "rockchip,rk3399-cru";
80 reg = <0xff760000 0x1000>; 89 reg = <0xff760000 0x1000>;
81 #clock-cells = <1>; 90 #clock-cells = <1>;
82 #reset-cells = <1>; 91 #reset-cells = <1>;
83 }; 92 };
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