1 # SPDX-License-Identifier: GPL-2.0-only OR BSD 2 %YAML 1.2 3 --- 4 $id: http://devicetree.org/schemas/clock/rockc 5 $schema: http://devicetree.org/meta-schemas/co 6 7 title: Rockchip rk3588 Family Clock and Reset 8 9 maintainers: 10 - Elaine Zhang <zhangqing@rock-chips.com> 11 - Heiko Stuebner <heiko@sntech.de> 12 13 description: | 14 The RK3588 clock controller generates the cl 15 controller for SoC peripherals. For example 16 PCLK_UART2, as well as SRST_P_UART2 and SRST 17 module. 18 Each clock is assigned an identifier and cli 19 to specify the clock which they consume. All 20 are defined as preprocessor macros in dt-bin 21 22 properties: 23 compatible: 24 enum: 25 - rockchip,rk3588-cru 26 27 reg: 28 maxItems: 1 29 30 "#clock-cells": 31 const: 1 32 33 "#reset-cells": 34 const: 1 35 36 clocks: 37 minItems: 2 38 maxItems: 2 39 40 clock-names: 41 items: 42 - const: xin24m 43 - const: xin32k 44 45 rockchip,grf: 46 $ref: /schemas/types.yaml#/definitions/pha 47 description: > 48 phandle to the syscon managing the "gene 49 for GRF muxes, if missing any muxes pres 50 available. 51 52 required: 53 - compatible 54 - reg 55 - "#clock-cells" 56 - "#reset-cells" 57 58 additionalProperties: false 59 60 examples: 61 - | 62 cru: clock-controller@fd7c0000 { 63 compatible = "rockchip,rk3588-cru"; 64 reg = <0xfd7c0000 0x5c000>; 65 #clock-cells = <1>; 66 #reset-cells = <1>; 67 };
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