1 # SPDX-License-Identifier: GPL-2.0-only OR BSD 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2 %YAML 1.2 2 %YAML 1.2
3 --- 3 ---
4 $id: http://devicetree.org/schemas/clock/rockc 4 $id: http://devicetree.org/schemas/clock/rockchip,rk3588-cru.yaml#
5 $schema: http://devicetree.org/meta-schemas/co 5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6 6
7 title: Rockchip rk3588 Family Clock and Reset 7 title: Rockchip rk3588 Family Clock and Reset Control Module
8 8
9 maintainers: 9 maintainers:
10 - Elaine Zhang <zhangqing@rock-chips.com> 10 - Elaine Zhang <zhangqing@rock-chips.com>
11 - Heiko Stuebner <heiko@sntech.de> 11 - Heiko Stuebner <heiko@sntech.de>
12 12
13 description: | 13 description: |
14 The RK3588 clock controller generates the cl 14 The RK3588 clock controller generates the clock and also implements a reset
15 controller for SoC peripherals. For example 15 controller for SoC peripherals. For example it provides SCLK_UART2 and
16 PCLK_UART2, as well as SRST_P_UART2 and SRST 16 PCLK_UART2, as well as SRST_P_UART2 and SRST_S_UART2 for the second UART
17 module. 17 module.
18 Each clock is assigned an identifier and cli 18 Each clock is assigned an identifier and client nodes can use this identifier
19 to specify the clock which they consume. All 19 to specify the clock which they consume. All available clock and reset IDs
20 are defined as preprocessor macros in dt-bin 20 are defined as preprocessor macros in dt-binding headers.
21 21
22 properties: 22 properties:
23 compatible: 23 compatible:
24 enum: 24 enum:
25 - rockchip,rk3588-cru 25 - rockchip,rk3588-cru
26 26
27 reg: 27 reg:
28 maxItems: 1 28 maxItems: 1
29 29
30 "#clock-cells": 30 "#clock-cells":
31 const: 1 31 const: 1
32 32
33 "#reset-cells": 33 "#reset-cells":
34 const: 1 34 const: 1
35 35
36 clocks: 36 clocks:
37 minItems: 2 37 minItems: 2
38 maxItems: 2 38 maxItems: 2
39 39
40 clock-names: 40 clock-names:
41 items: 41 items:
42 - const: xin24m 42 - const: xin24m
43 - const: xin32k 43 - const: xin32k
44 44
>> 45 assigned-clocks: true
>> 46
>> 47 assigned-clock-rates: true
>> 48
45 rockchip,grf: 49 rockchip,grf:
46 $ref: /schemas/types.yaml#/definitions/pha 50 $ref: /schemas/types.yaml#/definitions/phandle
47 description: > 51 description: >
48 phandle to the syscon managing the "gene 52 phandle to the syscon managing the "general register files". It is used
49 for GRF muxes, if missing any muxes pres 53 for GRF muxes, if missing any muxes present in the GRF will not be
50 available. 54 available.
51 55
52 required: 56 required:
53 - compatible 57 - compatible
54 - reg 58 - reg
55 - "#clock-cells" 59 - "#clock-cells"
56 - "#reset-cells" 60 - "#reset-cells"
57 61
58 additionalProperties: false 62 additionalProperties: false
59 63
60 examples: 64 examples:
61 - | 65 - |
62 cru: clock-controller@fd7c0000 { 66 cru: clock-controller@fd7c0000 {
63 compatible = "rockchip,rk3588-cru"; 67 compatible = "rockchip,rk3588-cru";
64 reg = <0xfd7c0000 0x5c000>; 68 reg = <0xfd7c0000 0x5c000>;
65 #clock-cells = <1>; 69 #clock-cells = <1>;
66 #reset-cells = <1>; 70 #reset-cells = <1>;
67 }; 71 };
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