1 # SPDX-License-Identifier: (GPL-2.0+ OR MIT) 1 # SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 %YAML 1.2 2 %YAML 1.2
3 --- 3 ---
4 $id: http://devicetree.org/schemas/clock/rockc 4 $id: http://devicetree.org/schemas/clock/rockchip,rv1108-cru.yaml#
5 $schema: http://devicetree.org/meta-schemas/co 5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6 6
7 title: Rockchip RV1108 Clock and Reset Unit (C 7 title: Rockchip RV1108 Clock and Reset Unit (CRU)
8 8
9 maintainers: 9 maintainers:
10 - Elaine Zhang <zhangqing@rock-chips.com> 10 - Elaine Zhang <zhangqing@rock-chips.com>
11 - Heiko Stuebner <heiko@sntech.de> 11 - Heiko Stuebner <heiko@sntech.de>
12 12
13 description: | 13 description: |
14 The RV1108 clock controller generates and su 14 The RV1108 clock controller generates and supplies clocks to various
15 controllers within the SoC and also implemen 15 controllers within the SoC and also implements a reset controller for SoC
16 peripherals. 16 peripherals.
17 Each clock is assigned an identifier and cli 17 Each clock is assigned an identifier and client nodes can use this identifier
18 to specify the clock which they consume. All 18 to specify the clock which they consume. All available clocks are defined as
19 preprocessor macros in the dt-bindings/clock 19 preprocessor macros in the dt-bindings/clock/rv1108-cru.h headers and can be
20 used in device tree sources. Similar macros 20 used in device tree sources. Similar macros exist for the reset sources in
21 these files. 21 these files.
22 There are several clocks that are generated 22 There are several clocks that are generated outside the SoC. It is expected
23 that they are defined using standard clock b 23 that they are defined using standard clock bindings with following
24 clock-output-names: 24 clock-output-names:
25 - "xin24m" - crystal input 25 - "xin24m" - crystal input - required
26 - "ext_vip" - external VIP clock 26 - "ext_vip" - external VIP clock - optional
27 - "ext_i2s" - external I2S clock 27 - "ext_i2s" - external I2S clock - optional
28 - "ext_gmac" - external GMAC clock 28 - "ext_gmac" - external GMAC clock - optional
29 - "hdmiphy" - external clock input derive 29 - "hdmiphy" - external clock input derived from HDMI PHY - optional
30 - "usbphy" - external clock input derive 30 - "usbphy" - external clock input derived from USB PHY - optional
31 31
32 properties: 32 properties:
33 compatible: 33 compatible:
34 enum: 34 enum:
35 - rockchip,rv1108-cru 35 - rockchip,rv1108-cru
36 36
37 reg: 37 reg:
38 maxItems: 1 38 maxItems: 1
39 39
40 "#clock-cells": 40 "#clock-cells":
41 const: 1 41 const: 1
42 42
43 "#reset-cells": 43 "#reset-cells":
44 const: 1 44 const: 1
45 45
46 clocks: 46 clocks:
47 maxItems: 1 47 maxItems: 1
48 48
49 clock-names: 49 clock-names:
50 const: xin24m 50 const: xin24m
51 51
52 rockchip,grf: 52 rockchip,grf:
53 $ref: /schemas/types.yaml#/definitions/pha 53 $ref: /schemas/types.yaml#/definitions/phandle
54 description: 54 description:
55 Phandle to the syscon managing the "gene 55 Phandle to the syscon managing the "general register files" (GRF),
56 if missing pll rates are not changeable, 56 if missing pll rates are not changeable, due to the missing pll
57 lock status. 57 lock status.
58 58
59 required: 59 required:
60 - compatible 60 - compatible
61 - reg 61 - reg
62 - "#clock-cells" 62 - "#clock-cells"
63 - "#reset-cells" 63 - "#reset-cells"
64 64
65 additionalProperties: false 65 additionalProperties: false
66 66
67 examples: 67 examples:
68 - | 68 - |
69 cru: clock-controller@20200000 { 69 cru: clock-controller@20200000 {
70 compatible = "rockchip,rv1108-cru"; 70 compatible = "rockchip,rv1108-cru";
71 reg = <0x20200000 0x1000>; 71 reg = <0x20200000 0x1000>;
72 rockchip,grf = <&grf>; 72 rockchip,grf = <&grf>;
73 #clock-cells = <1>; 73 #clock-cells = <1>;
74 #reset-cells = <1>; 74 #reset-cells = <1>;
75 }; 75 };
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