1 Binding for a Clockgen hardware block found on 1 Binding for a Clockgen hardware block found on
2 certain STMicroelectronics consumer electronic 2 certain STMicroelectronics consumer electronics SoC devices.
3 3
4 A Clockgen node can contain pll, diviser or mu 4 A Clockgen node can contain pll, diviser or multiplexer nodes.
5 5
6 We will find only the base address of the Cloc 6 We will find only the base address of the Clockgen, this base
7 address is common of all subnode. 7 address is common of all subnode.
8 8
9 clockgen_node { 9 clockgen_node {
10 reg = <>; 10 reg = <>;
11 11
12 pll_node { 12 pll_node {
13 ... 13 ...
14 }; 14 };
15 15
16 quadfs_node { 16 quadfs_node {
17 ... 17 ...
18 }; 18 };
19 19
20 mux_node { 20 mux_node {
21 ... 21 ...
22 }; 22 };
23 23
24 flexgen_node { 24 flexgen_node {
25 ... 25 ...
26 }; 26 };
27 ... 27 ...
28 }; 28 };
29 29
30 This binding uses the common clock binding[1]. 30 This binding uses the common clock binding[1].
31 Each subnode should use the binding described 31 Each subnode should use the binding described in [2]..[7]
32 32
33 [1] Documentation/devicetree/bindings/clock/cl 33 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
34 [3] Documentation/devicetree/bindings/clock/st 34 [3] Documentation/devicetree/bindings/clock/st/st,clkgen-mux.txt
35 [4] Documentation/devicetree/bindings/clock/st 35 [4] Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt
36 [7] Documentation/devicetree/bindings/clock/st 36 [7] Documentation/devicetree/bindings/clock/st/st,quadfs.txt
37 [8] Documentation/devicetree/bindings/clock/st 37 [8] Documentation/devicetree/bindings/clock/st/st,flexgen.txt
38 38
39 39
40 Required properties: 40 Required properties:
41 - reg : A Base address and length of the regis 41 - reg : A Base address and length of the register set.
42 42
43 Example: 43 Example:
44 44
45 clockgen-a@90ff000 { 45 clockgen-a@90ff000 {
46 compatible = "st,clkgen-c32"; 46 compatible = "st,clkgen-c32";
47 reg = <0x90ff000 0x1000>; 47 reg = <0x90ff000 0x1000>;
48 48
49 clk_s_a0_pll: clk-s-a0-pll { 49 clk_s_a0_pll: clk-s-a0-pll {
50 #clock-cells = <1>; 50 #clock-cells = <1>;
51 compatible = "st,clkge 51 compatible = "st,clkgen-pll0";
52 52
53 clocks = <&clk_sysin>; 53 clocks = <&clk_sysin>;
54 54
55 clock-output-names = " 55 clock-output-names = "clk-s-a0-pll-ofd-0";
56 }; 56 };
57 57
58 clk_s_a0_flexgen: clk-s-a0-fle 58 clk_s_a0_flexgen: clk-s-a0-flexgen {
59 compatible = "st,flexg 59 compatible = "st,flexgen";
60 60
61 #clock-cells = <1>; 61 #clock-cells = <1>;
62 62
63 clocks = <&clk_s_a0_pl 63 clocks = <&clk_s_a0_pll 0>,
64 <&clk_sysin>; 64 <&clk_sysin>;
65 65
66 clock-output-names = " 66 clock-output-names = "clk-ic-lmi0";
67 }; 67 };
68 }; 68 };
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