1 # SPDX-License-Identifier: GPL-2.0-only OR BSD
2 %YAML 1.2
3 ---
4 $id: http://devicetree.org/schemas/clock/starf
5 $schema: http://devicetree.org/meta-schemas/co
6
7 title: StarFive JH7110 PLL Clock Generator
8
9 description:
10 These PLLs are high speed, low jitter freque
11 Each PLL works in integer mode or fraction m
12 registers in the sys syscon. So the PLLs nod
13 SYS-SYSCON node.
14 The formula for calculating frequency is
15 Fvco = Fref * (NI + NF) / M / Q1
16
17 maintainers:
18 - Xingyu Wu <xingyu.wu@starfivetech.com>
19
20 properties:
21 compatible:
22 const: starfive,jh7110-pll
23
24 clocks:
25 maxItems: 1
26 description: Main Oscillator (24 MHz)
27
28 '#clock-cells':
29 const: 1
30 description:
31 See <dt-bindings/clock/starfive,jh7110-c
32
33 required:
34 - compatible
35 - clocks
36 - '#clock-cells'
37
38 additionalProperties: false
39
40 examples:
41 - |
42 clock-controller {
43 compatible = "starfive,jh7110-pll";
44 clocks = <&osc>;
45 #clock-cells = <1>;
46 };
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