1 # SPDX-License-Identifier: (GPL-2.0-only OR BS
2 %YAML 1.2
3 ---
4 $id: http://devicetree.org/schemas/clock/ti,cd
5 $schema: http://devicetree.org/meta-schemas/co
6
7 title: TI CDCE913/925/937/949 programmable I2C
8
9 maintainers:
10 - Alexander Stein <alexander.stein@ew.tq-grou
11
12 description: |
13 Flexible Low Power LVCMOS Clock Generator wi
14
15 - CDCE(L)913: 1-PLL, 3 Outputs https://www.t
16 - CDCE(L)925: 2-PLL, 5 Outputs https://www.t
17 - CDCE(L)937: 3-PLL, 7 Outputs https://www.t
18 - CDCE(L)949: 4-PLL, 9 Outputs https://www.t
19
20 properties:
21 compatible:
22 enum:
23 - ti,cdce913
24 - ti,cdce925
25 - ti,cdce937
26 - ti,cdce949
27
28 reg:
29 maxItems: 1
30
31 clocks:
32 items:
33 - description: fixed parent clock
34
35 "#clock-cells":
36 const: 1
37
38 vdd-supply:
39 description: Regulator that provides 1.8V
40
41 vddout-supply:
42 description: |
43 Regulator that provides Vddout power sup
44 non-L variant: 2.5V or 3.3V for
45 L variant: 1.8V for
46
47 xtal-load-pf:
48 $ref: /schemas/types.yaml#/definitions/uin
49 description: |
50 Crystal load-capacitor value to fine-tun
51 board, or to compensate for external inf
52
53 patternProperties:
54 "^PLL[1-4]$":
55 type: object
56 description: |
57 optional child node can be used to speci
58 spectrum clocking parameters for a board
59
60 additionalProperties: false
61
62 properties:
63 spread-spectrum:
64 $ref: /schemas/types.yaml#/definitions
65 description: SSC mode as defined in th
66
67 spread-spectrum-center:
68 type: boolean
69 description: |
70 Use "centered" mode instead of "max"
71 present, the clock runs at the reque
72 Otherwise the requested frequency is
73 SCC range.
74
75 required:
76 - compatible
77 - reg
78 - clocks
79 - "#clock-cells"
80
81 additionalProperties: false
82
83 examples:
84 - |
85 i2c {
86 #address-cells = <1>;
87 #size-cells = <0>;
88
89 cdce925: clock-controller@64 {
90 compatible = "ti,cdce925";
91 reg = <0x64>;
92 clocks = <&xtal_27Mhz>;
93 #clock-cells = <1>;
94 xtal-load-pf = <5>;
95 vdd-supply = <®_1v8>;
96 vddout-supply = <®_3v3>;
97 /* PLL options to get SSC 1% cente
98 PLL2 {
99 spread-spectrum = <4>;
100 spread-spectrum-center;
101 };
102 };
103 };
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