1 Binding for TI divider clock
2
3 This binding uses the common clock binding[1].
4 register-mapped adjustable clock rate divider
5 only one input clock or parent. By default th
6 the register is one less than the actual divis
7
8 register value actual divisor value
9 0 1
10 1 2
11 2 3
12
13 This assumption may be modified by the followi
14
15 ti,index-starts-at-one - valid divisor values
16 of 0. E.g:
17 register value actual divisor value
18 1 1
19 2 2
20 3 3
21
22 ti,index-power-of-two - valid divisor values a
23 register value actual divisor value
24 0 1
25 1 2
26 2 4
27
28 Additionally an array of valid dividers may be
29
30 ti,dividers = <4>, <8>, <0>, <16>;
31
32 Which will map the resulting values to a divis
33 register value actual divisor value
34 0 4
35 1 8
36 2 <invalid divisor, skip
37 3 16
38
39 Any zero value in this array means the corresp
40 and must not be used.
41
42 The binding must also provide the register to
43 unless the divider array is provided, min and
44 the number of bits to shift that mask, if nece
45 is missing it is the same as supplying a zero
46
47 This binding can also optionally provide suppo
48 feature, see [2].
49
50 [1] Documentation/devicetree/bindings/clock/cl
51 [2] Documentation/devicetree/bindings/clock/ti
52
53 Required properties:
54 - compatible : shall be "ti,divider-clock" or
55 - #clock-cells : from common clock binding; sh
56 - clocks : link to phandle of parent clock
57 - reg : offset for register controlling adjust
58
59 Optional properties:
60 - clock-output-names : from common clock bindi
61 - ti,dividers : array of integers defining div
62 - ti,bit-shift : number of bits to shift the d
63 - ti,min-div : min divisor for dividing the in
64 needed if the first divisor is offset from t
65 - ti,max-div : max divisor for dividing the in
66 if ti,dividers is not defined.
67 - ti,index-starts-at-one : valid divisor progr
68 only valid if ti,dividers is not defined.
69 - ti,index-power-of-two : valid divisor progra
70 only valid if ti,dividers is not defined.
71 - ti,autoidle-shift : bit shift of the autoidl
72 see [2]
73 - ti,invert-autoidle-bit : autoidle is enabled
74 see [2]
75 - ti,set-rate-parent : clk_set_rate is propaga
76 - ti,latch-bit : latch the divider value to HW
77 access requires this. As an example dra76x D
78 such behavior.
79
80 Examples:
81 dpll_usb_m2_ck: dpll_usb_m2_ck@4a008190 {
82 #clock-cells = <0>;
83 compatible = "ti,divider-clock";
84 clocks = <&dpll_usb_ck>;
85 ti,max-div = <127>;
86 reg = <0x190>;
87 ti,index-starts-at-one;
88 };
89
90 aess_fclk: aess_fclk@4a004528 {
91 #clock-cells = <0>;
92 compatible = "ti,divider-clock";
93 clocks = <&abe_clk>;
94 ti,bit-shift = <24>;
95 reg = <0x528>;
96 ti,max-div = <2>;
97 };
98
99 dpll_core_m3x2_div_ck: dpll_core_m3x2_div_ck {
100 #clock-cells = <0>;
101 compatible = "ti,composite-divider-clo
102 clocks = <&dpll_core_x2_ck>;
103 ti,max-div = <31>;
104 reg = <0x0134>;
105 ti,index-starts-at-one;
106 };
107
108 ssi_ssr_div_fck_3430es2: ssi_ssr_div_fck_3430e
109 #clock-cells = <0>;
110 compatible = "ti,composite-divider-clo
111 clocks = <&corex2_fck>;
112 ti,bit-shift = <8>;
113 reg = <0x0a40>;
114 ti,dividers = <0>, <1>, <2>, <3>, <4>,
115 };
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