1 Binding for TI divider clock 1 Binding for TI divider clock
2 2
>> 3 Binding status: Unstable - ABI compatibility may be broken in the future
>> 4
3 This binding uses the common clock binding[1]. 5 This binding uses the common clock binding[1]. It assumes a
4 register-mapped adjustable clock rate divider 6 register-mapped adjustable clock rate divider that does not gate and has
5 only one input clock or parent. By default th 7 only one input clock or parent. By default the value programmed into
6 the register is one less than the actual divis 8 the register is one less than the actual divisor value. E.g:
7 9
8 register value actual divisor value 10 register value actual divisor value
9 0 1 11 0 1
10 1 2 12 1 2
11 2 3 13 2 3
12 14
13 This assumption may be modified by the followi 15 This assumption may be modified by the following optional properties:
14 16
15 ti,index-starts-at-one - valid divisor values 17 ti,index-starts-at-one - valid divisor values start at 1, not the default
16 of 0. E.g: 18 of 0. E.g:
17 register value actual divisor value 19 register value actual divisor value
18 1 1 20 1 1
19 2 2 21 2 2
20 3 3 22 3 3
21 23
22 ti,index-power-of-two - valid divisor values a 24 ti,index-power-of-two - valid divisor values are powers of two. E.g:
23 register value actual divisor value 25 register value actual divisor value
24 0 1 26 0 1
25 1 2 27 1 2
26 2 4 28 2 4
27 29
28 Additionally an array of valid dividers may be 30 Additionally an array of valid dividers may be supplied like so:
29 31
30 ti,dividers = <4>, <8>, <0>, <16>; 32 ti,dividers = <4>, <8>, <0>, <16>;
31 33
32 Which will map the resulting values to a divis 34 Which will map the resulting values to a divisor table by their index:
33 register value actual divisor value 35 register value actual divisor value
34 0 4 36 0 4
35 1 8 37 1 8
36 2 <invalid divisor, skip 38 2 <invalid divisor, skipped>
37 3 16 39 3 16
38 40
39 Any zero value in this array means the corresp 41 Any zero value in this array means the corresponding bit-value is invalid
40 and must not be used. 42 and must not be used.
41 43
42 The binding must also provide the register to 44 The binding must also provide the register to control the divider and
43 unless the divider array is provided, min and 45 unless the divider array is provided, min and max dividers. Optionally
44 the number of bits to shift that mask, if nece 46 the number of bits to shift that mask, if necessary. If the shift value
45 is missing it is the same as supplying a zero 47 is missing it is the same as supplying a zero shift.
46 48
47 This binding can also optionally provide suppo 49 This binding can also optionally provide support to the hardware autoidle
48 feature, see [2]. 50 feature, see [2].
49 51
50 [1] Documentation/devicetree/bindings/clock/cl 52 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
51 [2] Documentation/devicetree/bindings/clock/ti 53 [2] Documentation/devicetree/bindings/clock/ti/autoidle.txt
52 54
53 Required properties: 55 Required properties:
54 - compatible : shall be "ti,divider-clock" or 56 - compatible : shall be "ti,divider-clock" or "ti,composite-divider-clock".
55 - #clock-cells : from common clock binding; sh 57 - #clock-cells : from common clock binding; shall be set to 0.
56 - clocks : link to phandle of parent clock 58 - clocks : link to phandle of parent clock
57 - reg : offset for register controlling adjust 59 - reg : offset for register controlling adjustable divider
58 60
59 Optional properties: 61 Optional properties:
60 - clock-output-names : from common clock bindi 62 - clock-output-names : from common clock binding.
61 - ti,dividers : array of integers defining div 63 - ti,dividers : array of integers defining divisors
62 - ti,bit-shift : number of bits to shift the d 64 - ti,bit-shift : number of bits to shift the divider value, defaults to 0
63 - ti,min-div : min divisor for dividing the in 65 - ti,min-div : min divisor for dividing the input clock rate, only
64 needed if the first divisor is offset from t 66 needed if the first divisor is offset from the default value (1)
65 - ti,max-div : max divisor for dividing the in 67 - ti,max-div : max divisor for dividing the input clock rate, only needed
66 if ti,dividers is not defined. 68 if ti,dividers is not defined.
67 - ti,index-starts-at-one : valid divisor progr 69 - ti,index-starts-at-one : valid divisor programming starts at 1, not zero,
68 only valid if ti,dividers is not defined. 70 only valid if ti,dividers is not defined.
69 - ti,index-power-of-two : valid divisor progra 71 - ti,index-power-of-two : valid divisor programming must be a power of two,
70 only valid if ti,dividers is not defined. 72 only valid if ti,dividers is not defined.
71 - ti,autoidle-shift : bit shift of the autoidl 73 - ti,autoidle-shift : bit shift of the autoidle enable bit for the clock,
72 see [2] 74 see [2]
73 - ti,invert-autoidle-bit : autoidle is enabled 75 - ti,invert-autoidle-bit : autoidle is enabled by setting the bit to 0,
74 see [2] 76 see [2]
75 - ti,set-rate-parent : clk_set_rate is propaga 77 - ti,set-rate-parent : clk_set_rate is propagated to parent
76 - ti,latch-bit : latch the divider value to HW <<
77 access requires this. As an example dra76x D <<
78 such behavior. <<
79 78
80 Examples: 79 Examples:
81 dpll_usb_m2_ck: dpll_usb_m2_ck@4a008190 { 80 dpll_usb_m2_ck: dpll_usb_m2_ck@4a008190 {
82 #clock-cells = <0>; 81 #clock-cells = <0>;
83 compatible = "ti,divider-clock"; 82 compatible = "ti,divider-clock";
84 clocks = <&dpll_usb_ck>; 83 clocks = <&dpll_usb_ck>;
85 ti,max-div = <127>; 84 ti,max-div = <127>;
86 reg = <0x190>; 85 reg = <0x190>;
87 ti,index-starts-at-one; 86 ti,index-starts-at-one;
88 }; 87 };
89 88
90 aess_fclk: aess_fclk@4a004528 { 89 aess_fclk: aess_fclk@4a004528 {
91 #clock-cells = <0>; 90 #clock-cells = <0>;
92 compatible = "ti,divider-clock"; 91 compatible = "ti,divider-clock";
93 clocks = <&abe_clk>; 92 clocks = <&abe_clk>;
94 ti,bit-shift = <24>; 93 ti,bit-shift = <24>;
95 reg = <0x528>; 94 reg = <0x528>;
96 ti,max-div = <2>; 95 ti,max-div = <2>;
97 }; 96 };
98 97
99 dpll_core_m3x2_div_ck: dpll_core_m3x2_div_ck { 98 dpll_core_m3x2_div_ck: dpll_core_m3x2_div_ck {
100 #clock-cells = <0>; 99 #clock-cells = <0>;
101 compatible = "ti,composite-divider-clo 100 compatible = "ti,composite-divider-clock";
102 clocks = <&dpll_core_x2_ck>; 101 clocks = <&dpll_core_x2_ck>;
103 ti,max-div = <31>; 102 ti,max-div = <31>;
104 reg = <0x0134>; 103 reg = <0x0134>;
105 ti,index-starts-at-one; 104 ti,index-starts-at-one;
106 }; 105 };
107 106
108 ssi_ssr_div_fck_3430es2: ssi_ssr_div_fck_3430e 107 ssi_ssr_div_fck_3430es2: ssi_ssr_div_fck_3430es2 {
109 #clock-cells = <0>; 108 #clock-cells = <0>;
110 compatible = "ti,composite-divider-clo 109 compatible = "ti,composite-divider-clock";
111 clocks = <&corex2_fck>; 110 clocks = <&corex2_fck>;
112 ti,bit-shift = <8>; 111 ti,bit-shift = <8>;
113 reg = <0x0a40>; 112 reg = <0x0a40>;
114 ti,dividers = <0>, <1>, <2>, <3>, <4>, 113 ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>;
115 }; 114 };
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