1 Binding for Texas Instruments DPLL clock. 1 Binding for Texas Instruments DPLL clock.
2 2
>> 3 Binding status: Unstable - ABI compatibility may be broken in the future
>> 4
3 This binding uses the common clock binding[1]. 5 This binding uses the common clock binding[1]. It assumes a
4 register-mapped DPLL with usually two selectab 6 register-mapped DPLL with usually two selectable input clocks
5 (reference clock and bypass clock), with digit 7 (reference clock and bypass clock), with digital phase locked
6 loop logic for multiplying the input clock to 8 loop logic for multiplying the input clock to a desired output
7 clock. This clock also typically supports diff 9 clock. This clock also typically supports different operation
8 modes (locked, low power stop etc.) This bindi 10 modes (locked, low power stop etc.) This binding has several
9 sub-types, which effectively result in slightl 11 sub-types, which effectively result in slightly different setup
10 for the actual DPLL clock. 12 for the actual DPLL clock.
11 13
12 [1] Documentation/devicetree/bindings/clock/cl 14 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
13 15
14 Required properties: 16 Required properties:
15 - compatible : shall be one of: 17 - compatible : shall be one of:
16 "ti,omap3-dpll-clock", 18 "ti,omap3-dpll-clock",
17 "ti,omap3-dpll-core-clock", 19 "ti,omap3-dpll-core-clock",
18 "ti,omap3-dpll-per-clock", 20 "ti,omap3-dpll-per-clock",
19 "ti,omap3-dpll-per-j-type-cloc 21 "ti,omap3-dpll-per-j-type-clock",
20 "ti,omap4-dpll-clock", 22 "ti,omap4-dpll-clock",
21 "ti,omap4-dpll-x2-clock", 23 "ti,omap4-dpll-x2-clock",
22 "ti,omap4-dpll-core-clock", 24 "ti,omap4-dpll-core-clock",
23 "ti,omap4-dpll-m4xen-clock", 25 "ti,omap4-dpll-m4xen-clock",
24 "ti,omap4-dpll-j-type-clock", 26 "ti,omap4-dpll-j-type-clock",
25 "ti,omap5-mpu-dpll-clock", 27 "ti,omap5-mpu-dpll-clock",
26 "ti,am3-dpll-no-gate-clock", 28 "ti,am3-dpll-no-gate-clock",
27 "ti,am3-dpll-j-type-clock", 29 "ti,am3-dpll-j-type-clock",
28 "ti,am3-dpll-no-gate-j-type-cl 30 "ti,am3-dpll-no-gate-j-type-clock",
29 "ti,am3-dpll-clock", 31 "ti,am3-dpll-clock",
30 "ti,am3-dpll-core-clock", 32 "ti,am3-dpll-core-clock",
31 "ti,am3-dpll-x2-clock", 33 "ti,am3-dpll-x2-clock",
32 "ti,omap2-dpll-core-clock", 34 "ti,omap2-dpll-core-clock",
33 35
34 - #clock-cells : from common clock binding; sh 36 - #clock-cells : from common clock binding; shall be set to 0.
35 - clocks : link phandles of parent clocks, fir 37 - clocks : link phandles of parent clocks, first entry lists reference clock
36 and second entry bypass clock 38 and second entry bypass clock
37 - reg : offsets for the register set for contr 39 - reg : offsets for the register set for controlling the DPLL.
38 Registers are listed in following order: 40 Registers are listed in following order:
39 "control" - contains the control regis 41 "control" - contains the control register base address
40 "idlest" - contains the idle status re 42 "idlest" - contains the idle status register base address
41 "mult-div1" - contains the multiplier 43 "mult-div1" - contains the multiplier / divider register base address
42 "autoidle" - contains the autoidle reg 44 "autoidle" - contains the autoidle register base address (optional)
43 "ssc-deltam" - DPLL supports spread sp 45 "ssc-deltam" - DPLL supports spread spectrum clocking (SSC), contains
44 the frequency spreading 46 the frequency spreading register base address (optional)
45 "ssc-modfreq" - DPLL supports spread s 47 "ssc-modfreq" - DPLL supports spread spectrum clocking (SSC), contains
46 the modulation frequen 48 the modulation frequency register base address
47 (optional) 49 (optional)
48 ti,am3-* dpll types do not have autoidle reg 50 ti,am3-* dpll types do not have autoidle register
49 ti,omap2-* dpll type does not support idlest 51 ti,omap2-* dpll type does not support idlest / autoidle registers
50 52
51 Optional properties: 53 Optional properties:
52 - DPLL mode setting - defining any one or more 54 - DPLL mode setting - defining any one or more of the following overrides
53 default setting. 55 default setting.
54 - ti,low-power-stop : DPLL supports lo 56 - ti,low-power-stop : DPLL supports low power stop mode, gating output
55 - ti,low-power-bypass : DPLL output ma 57 - ti,low-power-bypass : DPLL output matches rate of parent bypass clock
56 - ti,lock : DPLL locks in programmed r 58 - ti,lock : DPLL locks in programmed rate
57 - ti,min-div : the minimum divisor to 59 - ti,min-div : the minimum divisor to start from to round the DPLL
58 target rate 60 target rate
59 - ti,ssc-deltam : DPLL supports spread 61 - ti,ssc-deltam : DPLL supports spread spectrum clocking, frequency
60 spreading in permill 62 spreading in permille (10th of a percent)
61 - ti,ssc-modfreq-hz : DPLL supports sp 63 - ti,ssc-modfreq-hz : DPLL supports spread spectrum clocking, spread
62 spectrum modulat 64 spectrum modulation frequency
63 - ti,ssc-downspread : DPLL supports sp 65 - ti,ssc-downspread : DPLL supports spread spectrum clocking, boolean
64 to enable the do 66 to enable the downspread feature
65 67
66 Examples: 68 Examples:
67 dpll_core_ck: dpll_core_ck@44e00490 { 69 dpll_core_ck: dpll_core_ck@44e00490 {
68 #clock-cells = <0>; 70 #clock-cells = <0>;
69 compatible = "ti,omap4-dpll-co 71 compatible = "ti,omap4-dpll-core-clock";
70 clocks = <&sys_clkin_ck>, <&sy 72 clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
71 reg = <0x490>, <0x45c>, <0x488 73 reg = <0x490>, <0x45c>, <0x488>, <0x468>;
72 }; 74 };
73 75
74 dpll2_ck: dpll2_ck@48004004 { 76 dpll2_ck: dpll2_ck@48004004 {
75 #clock-cells = <0>; 77 #clock-cells = <0>;
76 compatible = "ti,omap3-dpll-cl 78 compatible = "ti,omap3-dpll-clock";
77 clocks = <&sys_ck>, <&dpll2_fc 79 clocks = <&sys_ck>, <&dpll2_fck>;
78 ti,low-power-stop; 80 ti,low-power-stop;
79 ti,low-power-bypass; 81 ti,low-power-bypass;
80 ti,lock; 82 ti,lock;
81 reg = <0x4>, <0x24>, <0x34>, < 83 reg = <0x4>, <0x24>, <0x34>, <0x40>;
82 }; 84 };
83 85
84 dpll_core_ck: dpll_core_ck@44e00490 { 86 dpll_core_ck: dpll_core_ck@44e00490 {
85 #clock-cells = <0>; 87 #clock-cells = <0>;
86 compatible = "ti,am3-dpll-core 88 compatible = "ti,am3-dpll-core-clock";
87 clocks = <&sys_clkin_ck>, <&sy 89 clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
88 reg = <0x90>, <0x5c>, <0x68>; 90 reg = <0x90>, <0x5c>, <0x68>;
89 }; 91 };
90 92
91 dpll_ck: dpll_ck { 93 dpll_ck: dpll_ck {
92 #clock-cells = <0>; 94 #clock-cells = <0>;
93 compatible = "ti,omap2-dpll-co 95 compatible = "ti,omap2-dpll-core-clock";
94 clocks = <&sys_ck>, <&sys_ck>; 96 clocks = <&sys_ck>, <&sys_ck>;
95 reg = <0x0500>, <0x0540>; 97 reg = <0x0500>, <0x0540>;
96 }; 98 };
97 99
98 dpll_disp_ck: dpll_disp_ck { 100 dpll_disp_ck: dpll_disp_ck {
99 #clock-cells = <0>; 101 #clock-cells = <0>;
100 compatible = "ti,am3-dpll-no-g 102 compatible = "ti,am3-dpll-no-gate-clock";
101 clocks = <&sys_clkin_ck>, <&sy 103 clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
102 reg = <0x0498>, <0x0448>, <0x0 104 reg = <0x0498>, <0x0448>, <0x0454>, <0x044c>, <0x0450>;
103 }; 105 };
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