1 # SPDX-License-Identifier: (GPL-2.0-only OR BS 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 %YAML 1.2 2 %YAML 1.2
3 --- 3 ---
4 $id: http://devicetree.org/schemas/clock/xlnx, 4 $id: http://devicetree.org/schemas/clock/xlnx,clocking-wizard.yaml#
5 $schema: http://devicetree.org/meta-schemas/co 5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6 6
7 title: Xilinx clocking wizard 7 title: Xilinx clocking wizard
8 8
9 maintainers: 9 maintainers:
10 - Shubhrajyoti Datta <shubhrajyoti.datta@amd. 10 - Shubhrajyoti Datta <shubhrajyoti.datta@amd.com>
11 11
12 description: 12 description:
13 The clocking wizard is a soft ip clocking bl 13 The clocking wizard is a soft ip clocking block of Xilinx versal. It
14 reads required input clock frequencies from 14 reads required input clock frequencies from the devicetree and acts as clock
15 clock output. 15 clock output.
16 16
17 properties: 17 properties:
18 compatible: 18 compatible:
19 enum: 19 enum:
20 - xlnx,clocking-wizard 20 - xlnx,clocking-wizard
21 - xlnx,clocking-wizard-v5.2 21 - xlnx,clocking-wizard-v5.2
22 - xlnx,clocking-wizard-v6.0 22 - xlnx,clocking-wizard-v6.0
23 - xlnx,versal-clk-wizard 23 - xlnx,versal-clk-wizard
24 24
25 25
26 reg: 26 reg:
27 maxItems: 1 27 maxItems: 1
28 28
29 "#clock-cells": 29 "#clock-cells":
30 const: 1 30 const: 1
31 31
32 clocks: 32 clocks:
33 items: 33 items:
34 - description: clock input 34 - description: clock input
35 - description: axi clock 35 - description: axi clock
36 36
37 clock-names: 37 clock-names:
38 items: 38 items:
39 - const: clk_in1 39 - const: clk_in1
40 - const: s_axi_aclk 40 - const: s_axi_aclk
41 41
42 42
43 xlnx,speed-grade: 43 xlnx,speed-grade:
44 $ref: /schemas/types.yaml#/definitions/uin 44 $ref: /schemas/types.yaml#/definitions/uint32
45 enum: [1, 2, 3] 45 enum: [1, 2, 3]
46 description: 46 description:
47 Speed grade of the device. Higher the sp 47 Speed grade of the device. Higher the speed grade faster is the FPGA device.
48 48
49 xlnx,nr-outputs: 49 xlnx,nr-outputs:
50 $ref: /schemas/types.yaml#/definitions/uin 50 $ref: /schemas/types.yaml#/definitions/uint32
51 minimum: 1 51 minimum: 1
52 maximum: 8 52 maximum: 8
53 description: 53 description:
54 Number of outputs. 54 Number of outputs.
55 55
56 required: 56 required:
57 - compatible 57 - compatible
58 - reg 58 - reg
59 - "#clock-cells" 59 - "#clock-cells"
60 - clocks 60 - clocks
61 - clock-names 61 - clock-names
62 - xlnx,speed-grade 62 - xlnx,speed-grade
63 - xlnx,nr-outputs 63 - xlnx,nr-outputs
64 64
65 additionalProperties: false 65 additionalProperties: false
66 66
67 examples: 67 examples:
68 - | 68 - |
69 clock-controller@b0000000 { 69 clock-controller@b0000000 {
70 compatible = "xlnx,clocking-wizard"; 70 compatible = "xlnx,clocking-wizard";
71 reg = <0xb0000000 0x10000>; 71 reg = <0xb0000000 0x10000>;
72 #clock-cells = <1>; 72 #clock-cells = <1>;
73 xlnx,speed-grade = <1>; 73 xlnx,speed-grade = <1>;
74 xlnx,nr-outputs = <6>; 74 xlnx,nr-outputs = <6>;
75 clock-names = "clk_in1", "s_axi_aclk"; 75 clock-names = "clk_in1", "s_axi_aclk";
76 clocks = <&clkc 15>, <&clkc 15>; 76 clocks = <&clkc 15>, <&clkc 15>;
77 }; 77 };
78 ... 78 ...
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