1 # SPDX-License-Identifier: (GPL-2.0-only OR BS 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 %YAML 1.2 2 %YAML 1.2
3 --- 3 ---
4 $id: http://devicetree.org/schemas/clock/xlnx, 4 $id: http://devicetree.org/schemas/clock/xlnx,clocking-wizard.yaml#
5 $schema: http://devicetree.org/meta-schemas/co 5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6 6
7 title: Xilinx clocking wizard 7 title: Xilinx clocking wizard
8 8
9 maintainers: 9 maintainers:
10 - Shubhrajyoti Datta <shubhrajyoti.datta@amd. 10 - Shubhrajyoti Datta <shubhrajyoti.datta@amd.com>
11 11
12 description: 12 description:
13 The clocking wizard is a soft ip clocking bl 13 The clocking wizard is a soft ip clocking block of Xilinx versal. It
14 reads required input clock frequencies from 14 reads required input clock frequencies from the devicetree and acts as clock
15 clock output. 15 clock output.
16 16
17 properties: 17 properties:
18 compatible: 18 compatible:
19 enum: 19 enum:
20 - xlnx,clocking-wizard 20 - xlnx,clocking-wizard
21 - xlnx,clocking-wizard-v5.2 21 - xlnx,clocking-wizard-v5.2
22 - xlnx,clocking-wizard-v6.0 22 - xlnx,clocking-wizard-v6.0
23 - xlnx,versal-clk-wizard <<
24 23
25 24
26 reg: 25 reg:
27 maxItems: 1 26 maxItems: 1
28 27
29 "#clock-cells": 28 "#clock-cells":
30 const: 1 29 const: 1
31 30
32 clocks: 31 clocks:
33 items: 32 items:
34 - description: clock input 33 - description: clock input
35 - description: axi clock 34 - description: axi clock
36 35
37 clock-names: 36 clock-names:
38 items: 37 items:
39 - const: clk_in1 38 - const: clk_in1
40 - const: s_axi_aclk 39 - const: s_axi_aclk
41 40
42 41
43 xlnx,speed-grade: 42 xlnx,speed-grade:
44 $ref: /schemas/types.yaml#/definitions/uin 43 $ref: /schemas/types.yaml#/definitions/uint32
45 enum: [1, 2, 3] 44 enum: [1, 2, 3]
46 description: 45 description:
47 Speed grade of the device. Higher the sp 46 Speed grade of the device. Higher the speed grade faster is the FPGA device.
48 47
49 xlnx,nr-outputs: 48 xlnx,nr-outputs:
50 $ref: /schemas/types.yaml#/definitions/uin 49 $ref: /schemas/types.yaml#/definitions/uint32
51 minimum: 1 50 minimum: 1
52 maximum: 8 51 maximum: 8
53 description: 52 description:
54 Number of outputs. 53 Number of outputs.
55 54
56 required: 55 required:
57 - compatible 56 - compatible
58 - reg 57 - reg
59 - "#clock-cells" 58 - "#clock-cells"
60 - clocks 59 - clocks
61 - clock-names 60 - clock-names
62 - xlnx,speed-grade 61 - xlnx,speed-grade
63 - xlnx,nr-outputs 62 - xlnx,nr-outputs
64 63
65 additionalProperties: false 64 additionalProperties: false
66 65
67 examples: 66 examples:
68 - | 67 - |
69 clock-controller@b0000000 { 68 clock-controller@b0000000 {
70 compatible = "xlnx,clocking-wizard"; 69 compatible = "xlnx,clocking-wizard";
71 reg = <0xb0000000 0x10000>; 70 reg = <0xb0000000 0x10000>;
72 #clock-cells = <1>; 71 #clock-cells = <1>;
73 xlnx,speed-grade = <1>; 72 xlnx,speed-grade = <1>;
74 xlnx,nr-outputs = <6>; 73 xlnx,nr-outputs = <6>;
75 clock-names = "clk_in1", "s_axi_aclk"; 74 clock-names = "clk_in1", "s_axi_aclk";
76 clocks = <&clkc 15>, <&clkc 15>; 75 clocks = <&clkc 15>, <&clkc 15>;
77 }; 76 };
78 ... 77 ...
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