1 Common properties 1 Common properties
2 ================= <<
3 2
4 Endianness !! 3 The ePAPR specification does not define any properties related to hardware
5 ---------- !! 4 byteswapping, but endianness issues show up frequently in porting Linux to
6 <<
7 The Devicetree Specification does not define a <<
8 byte swapping, but endianness issues show up f <<
9 different machine types. This document attemp 5 different machine types. This document attempts to provide a consistent
10 way of handling byte swapping across drivers. !! 6 way of handling byteswapping across drivers.
11 7
12 Optional properties: 8 Optional properties:
13 - big-endian: Boolean; force big endian regis 9 - big-endian: Boolean; force big endian register accesses
14 unconditionally (e.g. ioread32be/iowrite32b 10 unconditionally (e.g. ioread32be/iowrite32be). Use this if you
15 know the peripheral always needs to be acce !! 11 know the peripheral always needs to be accessed in BE mode.
16 - little-endian: Boolean; force little endian 12 - little-endian: Boolean; force little endian register accesses
17 unconditionally (e.g. readl/writel). Use t 13 unconditionally (e.g. readl/writel). Use this if you know the
18 peripheral always needs to be accessed in l !! 14 peripheral always needs to be accessed in LE mode.
19 - native-endian: Boolean; always use register 15 - native-endian: Boolean; always use register accesses matched to the
20 endianness of the kernel binary (e.g. LE vm 16 endianness of the kernel binary (e.g. LE vmlinux -> readl/writel,
21 BE vmlinux -> ioread32be/iowrite32be). In !! 17 BE vmlinux -> ioread32be/iowrite32be). In this case no byteswaps
22 will ever be performed. Use this if the ha 18 will ever be performed. Use this if the hardware "self-adjusts"
23 register endianness based on the CPU's conf 19 register endianness based on the CPU's configured endianness.
24 20
25 If a binding supports these properties, then t 21 If a binding supports these properties, then the binding should also
26 specify the default behavior if none of these 22 specify the default behavior if none of these properties are present.
27 In such cases, little-endian is the preferred 23 In such cases, little-endian is the preferred default, but it is not
28 a requirement. Some implementations assume th !! 24 a requirement. The of_device_is_big_endian() and of_fdt_is_big_endian()
29 the default, because most existing (PCI-based) !! 25 helper functions do assume that little-endian is the default, because
30 default to LE for their MMIO accesses. !! 26 most existing (PCI-based) drivers implicitly default to LE by using
>> 27 readl/writel for MMIO accesses.
31 28
32 Examples: 29 Examples:
33 Scenario 1 : CPU in LE mode & device in LE mod 30 Scenario 1 : CPU in LE mode & device in LE mode.
34 dev: dev@40031000 { 31 dev: dev@40031000 {
35 compatible = "name"; 32 compatible = "name";
36 reg = <0x40031000 0x1000>; 33 reg = <0x40031000 0x1000>;
37 ... 34 ...
38 native-endian; 35 native-endian;
39 }; 36 };
40 37
41 Scenario 2 : CPU in LE mode & device in BE mod 38 Scenario 2 : CPU in LE mode & device in BE mode.
42 dev: dev@40031000 { 39 dev: dev@40031000 {
43 compatible = "name"; 40 compatible = "name";
44 reg = <0x40031000 0x1000>; 41 reg = <0x40031000 0x1000>;
45 ... 42 ...
46 big-endian; 43 big-endian;
47 }; 44 };
48 45
49 Scenario 3 : CPU in BE mode & device in BE mod 46 Scenario 3 : CPU in BE mode & device in BE mode.
50 dev: dev@40031000 { 47 dev: dev@40031000 {
51 compatible = "name"; 48 compatible = "name";
52 reg = <0x40031000 0x1000>; 49 reg = <0x40031000 0x1000>;
53 ... 50 ...
54 native-endian; 51 native-endian;
55 }; 52 };
56 53
57 Scenario 4 : CPU in BE mode & device in LE mod 54 Scenario 4 : CPU in BE mode & device in LE mode.
58 dev: dev@40031000 { 55 dev: dev@40031000 {
59 compatible = "name"; 56 compatible = "name";
60 reg = <0x40031000 0x1000>; 57 reg = <0x40031000 0x1000>;
61 ... 58 ...
62 little-endian; 59 little-endian;
63 }; <<
64 <<
65 Daisy-chained devices <<
66 --------------------- <<
67 <<
68 Many serially-attached GPIO and IIO devices ar <<
69 host controller, a daisy-chain appears as a si <<
70 of inputs and outputs it provides is the sum o <<
71 by all of its devices. The driver needs to kn <<
72 daisy-chain comprises to determine the amount <<
73 inputs and outputs to register and so on. <<
74 <<
75 Optional properties: <<
76 - #daisy-chained-devices: Number of devices i <<
77 <<
78 Example: <<
79 gpio@0 { <<
80 compatible = "name"; <<
81 reg = <0>; <<
82 gpio-controller; <<
83 #gpio-cells = <2>; <<
84 #daisy-chained-devices = <3>; <<
85 }; 60 };
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