1 Generic cpufreq driver 1 Generic cpufreq driver
2 2
3 It is a generic DT based cpufreq driver for fr 3 It is a generic DT based cpufreq driver for frequency management. It supports
4 both uniprocessor (UP) and symmetric multiproc 4 both uniprocessor (UP) and symmetric multiprocessor (SMP) systems which share
5 clock and voltage across all CPUs. 5 clock and voltage across all CPUs.
6 6
7 Both required and optional properties listed b 7 Both required and optional properties listed below must be defined
8 under node /cpus/cpu@0. 8 under node /cpus/cpu@0.
9 9
10 Required properties: 10 Required properties:
11 - None 11 - None
12 12
13 Optional properties: 13 Optional properties:
14 - operating-points: Refer to Documentation/dev 14 - operating-points: Refer to Documentation/devicetree/bindings/opp/opp-v1.yaml for
15 details. OPPs *must* be supplied either via 15 details. OPPs *must* be supplied either via DT, i.e. this property, or
16 populated at runtime. 16 populated at runtime.
17 - clock-latency: Specify the possible maximum 17 - clock-latency: Specify the possible maximum transition latency for clock,
18 in unit of nanoseconds. 18 in unit of nanoseconds.
19 - voltage-tolerance: Specify the CPU voltage t 19 - voltage-tolerance: Specify the CPU voltage tolerance in percentage.
20 - #cooling-cells: 20 - #cooling-cells:
21 Please refer to 21 Please refer to
22 Documentation/devicetree/bindings/thermal 22 Documentation/devicetree/bindings/thermal/thermal-cooling-devices.yaml.
23 23
24 Examples: 24 Examples:
25 25
26 cpus { 26 cpus {
27 #address-cells = <1>; 27 #address-cells = <1>;
28 #size-cells = <0>; 28 #size-cells = <0>;
29 29
30 cpu@0 { 30 cpu@0 {
31 compatible = "arm,cortex-a9"; 31 compatible = "arm,cortex-a9";
32 reg = <0>; 32 reg = <0>;
33 next-level-cache = <&L2>; 33 next-level-cache = <&L2>;
34 operating-points = < 34 operating-points = <
35 /* kHz uV */ 35 /* kHz uV */
36 792000 1100000 36 792000 1100000
37 396000 950000 37 396000 950000
38 198000 850000 38 198000 850000
39 >; 39 >;
40 clock-latency = <61036>; /* tw 40 clock-latency = <61036>; /* two CLK32 periods */
41 #cooling-cells = <2>; 41 #cooling-cells = <2>;
42 }; 42 };
43 43
44 cpu@1 { 44 cpu@1 {
45 compatible = "arm,cortex-a9"; 45 compatible = "arm,cortex-a9";
46 reg = <1>; 46 reg = <1>;
47 next-level-cache = <&L2>; 47 next-level-cache = <&L2>;
48 }; 48 };
49 49
50 cpu@2 { 50 cpu@2 {
51 compatible = "arm,cortex-a9"; 51 compatible = "arm,cortex-a9";
52 reg = <2>; 52 reg = <2>;
53 next-level-cache = <&L2>; 53 next-level-cache = <&L2>;
54 }; 54 };
55 55
56 cpu@3 { 56 cpu@3 {
57 compatible = "arm,cortex-a9"; 57 compatible = "arm,cortex-a9";
58 reg = <3>; 58 reg = <3>;
59 next-level-cache = <&L2>; 59 next-level-cache = <&L2>;
60 }; 60 };
61 }; 61 };
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