1 Binding for MediaTek's CPUFreq driver 1 Binding for MediaTek's CPUFreq driver
2 ===================================== 2 =====================================
3 3
4 Required properties: 4 Required properties:
5 - clocks: A list of phandle + clock-specifier 5 - clocks: A list of phandle + clock-specifier pairs for the clocks listed in clock names.
6 - clock-names: Should contain the following: 6 - clock-names: Should contain the following:
7 "cpu" - The multiplexer for 7 "cpu" - The multiplexer for clock input of CPU cluster.
8 "intermediate" - A parent of "cpu" cl 8 "intermediate" - A parent of "cpu" clock which is used as "intermediate" clock
9 source (usually MAIN 9 source (usually MAINPLL) when the original CPU PLL is under
10 transition and not s 10 transition and not stable yet.
11 Please refer to Documentation/devicetr 11 Please refer to Documentation/devicetree/bindings/clock/clock-bindings.txt for
12 generic clock consumer properties. 12 generic clock consumer properties.
13 - operating-points-v2: Please refer to Documen 13 - operating-points-v2: Please refer to Documentation/devicetree/bindings/opp/opp-v2.yaml
14 for detail. 14 for detail.
15 - proc-supply: Regulator for Vproc of CPU clus 15 - proc-supply: Regulator for Vproc of CPU cluster.
16 16
17 Optional properties: 17 Optional properties:
18 - sram-supply: Regulator for Vsram of CPU clus 18 - sram-supply: Regulator for Vsram of CPU cluster. When present, the cpufreq driver
19 needs to do "voltage tracking" 19 needs to do "voltage tracking" to step by step scale up/down Vproc and
20 Vsram to fit SoC specific needs 20 Vsram to fit SoC specific needs. When absent, the voltage scaling
21 flow is handled by hardware, he 21 flow is handled by hardware, hence no software "voltage tracking" is
22 needed. 22 needed.
23 - mediatek,cci: 23 - mediatek,cci:
24 Used to confirm the link status betwee 24 Used to confirm the link status between cpufreq and mediatek cci. Because
25 cpufreq and mediatek cci could share t 25 cpufreq and mediatek cci could share the same regulator in some MediaTek SoCs.
26 To prevent the issue of high frequency 26 To prevent the issue of high frequency and low voltage, we need to use this
27 property to make sure mediatek cci is 27 property to make sure mediatek cci is ready.
28 For details of mediatek cci, please re 28 For details of mediatek cci, please refer to
29 Documentation/devicetree/bindings/inte 29 Documentation/devicetree/bindings/interconnect/mediatek,cci.yaml
30 - #cooling-cells: 30 - #cooling-cells:
31 For details, please refer to 31 For details, please refer to
32 Documentation/devicetree/bindings/ther 32 Documentation/devicetree/bindings/thermal/thermal-cooling-devices.yaml
33 33
34 Example 1 (MT7623 SoC): 34 Example 1 (MT7623 SoC):
35 35
36 cpu_opp_table: opp_table { 36 cpu_opp_table: opp_table {
37 compatible = "operating-points 37 compatible = "operating-points-v2";
38 opp-shared; 38 opp-shared;
39 39
40 opp-598000000 { 40 opp-598000000 {
41 opp-hz = /bits/ 64 <59 41 opp-hz = /bits/ 64 <598000000>;
42 opp-microvolt = <10500 42 opp-microvolt = <1050000>;
43 }; 43 };
44 44
45 opp-747500000 { 45 opp-747500000 {
46 opp-hz = /bits/ 64 <74 46 opp-hz = /bits/ 64 <747500000>;
47 opp-microvolt = <10500 47 opp-microvolt = <1050000>;
48 }; 48 };
49 49
50 opp-1040000000 { 50 opp-1040000000 {
51 opp-hz = /bits/ 64 <10 51 opp-hz = /bits/ 64 <1040000000>;
52 opp-microvolt = <11500 52 opp-microvolt = <1150000>;
53 }; 53 };
54 54
55 opp-1196000000 { 55 opp-1196000000 {
56 opp-hz = /bits/ 64 <11 56 opp-hz = /bits/ 64 <1196000000>;
57 opp-microvolt = <12000 57 opp-microvolt = <1200000>;
58 }; 58 };
59 59
60 opp-1300000000 { 60 opp-1300000000 {
61 opp-hz = /bits/ 64 <13 61 opp-hz = /bits/ 64 <1300000000>;
62 opp-microvolt = <13000 62 opp-microvolt = <1300000>;
63 }; 63 };
64 }; 64 };
65 65
66 cpu0: cpu@0 { 66 cpu0: cpu@0 {
67 device_type = "cpu"; 67 device_type = "cpu";
68 compatible = "arm,cortex-a7"; 68 compatible = "arm,cortex-a7";
69 reg = <0x0>; 69 reg = <0x0>;
70 clocks = <&infracfg CLK_INFRA_ 70 clocks = <&infracfg CLK_INFRA_CPUSEL>,
71 <&apmixedsys CLK_APMI 71 <&apmixedsys CLK_APMIXED_MAINPLL>;
72 clock-names = "cpu", "intermed 72 clock-names = "cpu", "intermediate";
73 operating-points-v2 = <&cpu_op 73 operating-points-v2 = <&cpu_opp_table>;
74 #cooling-cells = <2>; 74 #cooling-cells = <2>;
75 }; 75 };
76 cpu@1 { 76 cpu@1 {
77 device_type = "cpu"; 77 device_type = "cpu";
78 compatible = "arm,cortex-a7"; 78 compatible = "arm,cortex-a7";
79 reg = <0x1>; 79 reg = <0x1>;
80 operating-points-v2 = <&cpu_op 80 operating-points-v2 = <&cpu_opp_table>;
81 }; 81 };
82 cpu@2 { 82 cpu@2 {
83 device_type = "cpu"; 83 device_type = "cpu";
84 compatible = "arm,cortex-a7"; 84 compatible = "arm,cortex-a7";
85 reg = <0x2>; 85 reg = <0x2>;
86 operating-points-v2 = <&cpu_op 86 operating-points-v2 = <&cpu_opp_table>;
87 }; 87 };
88 cpu@3 { 88 cpu@3 {
89 device_type = "cpu"; 89 device_type = "cpu";
90 compatible = "arm,cortex-a7"; 90 compatible = "arm,cortex-a7";
91 reg = <0x3>; 91 reg = <0x3>;
92 operating-points-v2 = <&cpu_op 92 operating-points-v2 = <&cpu_opp_table>;
93 }; 93 };
94 94
95 Example 2 (MT8173 SoC): 95 Example 2 (MT8173 SoC):
96 cpu_opp_table_a: opp_table_a { 96 cpu_opp_table_a: opp_table_a {
97 compatible = "operating-points 97 compatible = "operating-points-v2";
98 opp-shared; 98 opp-shared;
99 99
100 opp-507000000 { 100 opp-507000000 {
101 opp-hz = /bits/ 64 <50 101 opp-hz = /bits/ 64 <507000000>;
102 opp-microvolt = <85900 102 opp-microvolt = <859000>;
103 }; 103 };
104 104
105 opp-702000000 { 105 opp-702000000 {
106 opp-hz = /bits/ 64 <70 106 opp-hz = /bits/ 64 <702000000>;
107 opp-microvolt = <90800 107 opp-microvolt = <908000>;
108 }; 108 };
109 109
110 opp-1001000000 { 110 opp-1001000000 {
111 opp-hz = /bits/ 64 <10 111 opp-hz = /bits/ 64 <1001000000>;
112 opp-microvolt = <98300 112 opp-microvolt = <983000>;
113 }; 113 };
114 114
115 opp-1105000000 { 115 opp-1105000000 {
116 opp-hz = /bits/ 64 <11 116 opp-hz = /bits/ 64 <1105000000>;
117 opp-microvolt = <10090 117 opp-microvolt = <1009000>;
118 }; 118 };
119 119
120 opp-1183000000 { 120 opp-1183000000 {
121 opp-hz = /bits/ 64 <11 121 opp-hz = /bits/ 64 <1183000000>;
122 opp-microvolt = <10280 122 opp-microvolt = <1028000>;
123 }; 123 };
124 124
125 opp-1404000000 { 125 opp-1404000000 {
126 opp-hz = /bits/ 64 <14 126 opp-hz = /bits/ 64 <1404000000>;
127 opp-microvolt = <10830 127 opp-microvolt = <1083000>;
128 }; 128 };
129 129
130 opp-1508000000 { 130 opp-1508000000 {
131 opp-hz = /bits/ 64 <15 131 opp-hz = /bits/ 64 <1508000000>;
132 opp-microvolt = <11090 132 opp-microvolt = <1109000>;
133 }; 133 };
134 134
135 opp-1573000000 { 135 opp-1573000000 {
136 opp-hz = /bits/ 64 <15 136 opp-hz = /bits/ 64 <1573000000>;
137 opp-microvolt = <11250 137 opp-microvolt = <1125000>;
138 }; 138 };
139 }; 139 };
140 140
141 cpu_opp_table_b: opp_table_b { 141 cpu_opp_table_b: opp_table_b {
142 compatible = "operating-points 142 compatible = "operating-points-v2";
143 opp-shared; 143 opp-shared;
144 144
145 opp-507000000 { 145 opp-507000000 {
146 opp-hz = /bits/ 64 <50 146 opp-hz = /bits/ 64 <507000000>;
147 opp-microvolt = <82800 147 opp-microvolt = <828000>;
148 }; 148 };
149 149
150 opp-702000000 { 150 opp-702000000 {
151 opp-hz = /bits/ 64 <70 151 opp-hz = /bits/ 64 <702000000>;
152 opp-microvolt = <86700 152 opp-microvolt = <867000>;
153 }; 153 };
154 154
155 opp-1001000000 { 155 opp-1001000000 {
156 opp-hz = /bits/ 64 <10 156 opp-hz = /bits/ 64 <1001000000>;
157 opp-microvolt = <92700 157 opp-microvolt = <927000>;
158 }; 158 };
159 159
160 opp-1209000000 { 160 opp-1209000000 {
161 opp-hz = /bits/ 64 <12 161 opp-hz = /bits/ 64 <1209000000>;
162 opp-microvolt = <96800 162 opp-microvolt = <968000>;
163 }; 163 };
164 164
165 opp-1404000000 { 165 opp-1404000000 {
166 opp-hz = /bits/ 64 <10 166 opp-hz = /bits/ 64 <1007000000>;
167 opp-microvolt = <10280 167 opp-microvolt = <1028000>;
168 }; 168 };
169 169
170 opp-1612000000 { 170 opp-1612000000 {
171 opp-hz = /bits/ 64 <16 171 opp-hz = /bits/ 64 <1612000000>;
172 opp-microvolt = <10490 172 opp-microvolt = <1049000>;
173 }; 173 };
174 174
175 opp-1807000000 { 175 opp-1807000000 {
176 opp-hz = /bits/ 64 <18 176 opp-hz = /bits/ 64 <1807000000>;
177 opp-microvolt = <10890 177 opp-microvolt = <1089000>;
178 }; 178 };
179 179
180 opp-1989000000 { 180 opp-1989000000 {
181 opp-hz = /bits/ 64 <19 181 opp-hz = /bits/ 64 <1989000000>;
182 opp-microvolt = <11250 182 opp-microvolt = <1125000>;
183 }; 183 };
184 }; 184 };
185 185
186 cpu0: cpu@0 { 186 cpu0: cpu@0 {
187 device_type = "cpu"; 187 device_type = "cpu";
188 compatible = "arm,cortex-a53"; 188 compatible = "arm,cortex-a53";
189 reg = <0x000>; 189 reg = <0x000>;
190 enable-method = "psci"; 190 enable-method = "psci";
191 cpu-idle-states = <&CPU_SLEEP_ 191 cpu-idle-states = <&CPU_SLEEP_0>;
192 clocks = <&infracfg CLK_INFRA_ 192 clocks = <&infracfg CLK_INFRA_CA53SEL>,
193 <&apmixedsys CLK_APMI 193 <&apmixedsys CLK_APMIXED_MAINPLL>;
194 clock-names = "cpu", "intermed 194 clock-names = "cpu", "intermediate";
195 operating-points-v2 = <&cpu_op 195 operating-points-v2 = <&cpu_opp_table_a>;
196 }; 196 };
197 197
198 cpu1: cpu@1 { 198 cpu1: cpu@1 {
199 device_type = "cpu"; 199 device_type = "cpu";
200 compatible = "arm,cortex-a53"; 200 compatible = "arm,cortex-a53";
201 reg = <0x001>; 201 reg = <0x001>;
202 enable-method = "psci"; 202 enable-method = "psci";
203 cpu-idle-states = <&CPU_SLEEP_ 203 cpu-idle-states = <&CPU_SLEEP_0>;
204 clocks = <&infracfg CLK_INFRA_ 204 clocks = <&infracfg CLK_INFRA_CA53SEL>,
205 <&apmixedsys CLK_APMI 205 <&apmixedsys CLK_APMIXED_MAINPLL>;
206 clock-names = "cpu", "intermed 206 clock-names = "cpu", "intermediate";
207 operating-points-v2 = <&cpu_op 207 operating-points-v2 = <&cpu_opp_table_a>;
208 }; 208 };
209 209
210 cpu2: cpu@100 { 210 cpu2: cpu@100 {
211 device_type = "cpu"; 211 device_type = "cpu";
212 compatible = "arm,cortex-a72"; 212 compatible = "arm,cortex-a72";
213 reg = <0x100>; 213 reg = <0x100>;
214 enable-method = "psci"; 214 enable-method = "psci";
215 cpu-idle-states = <&CPU_SLEEP_ 215 cpu-idle-states = <&CPU_SLEEP_0>;
216 clocks = <&infracfg CLK_INFRA_ 216 clocks = <&infracfg CLK_INFRA_CA72SEL>,
217 <&apmixedsys CLK_APMI 217 <&apmixedsys CLK_APMIXED_MAINPLL>;
218 clock-names = "cpu", "intermed 218 clock-names = "cpu", "intermediate";
219 operating-points-v2 = <&cpu_op 219 operating-points-v2 = <&cpu_opp_table_b>;
220 }; 220 };
221 221
222 cpu3: cpu@101 { 222 cpu3: cpu@101 {
223 device_type = "cpu"; 223 device_type = "cpu";
224 compatible = "arm,cortex-a72"; 224 compatible = "arm,cortex-a72";
225 reg = <0x101>; 225 reg = <0x101>;
226 enable-method = "psci"; 226 enable-method = "psci";
227 cpu-idle-states = <&CPU_SLEEP_ 227 cpu-idle-states = <&CPU_SLEEP_0>;
228 clocks = <&infracfg CLK_INFRA_ 228 clocks = <&infracfg CLK_INFRA_CA72SEL>,
229 <&apmixedsys CLK_APMI 229 <&apmixedsys CLK_APMIXED_MAINPLL>;
230 clock-names = "cpu", "intermed 230 clock-names = "cpu", "intermediate";
231 operating-points-v2 = <&cpu_op 231 operating-points-v2 = <&cpu_opp_table_b>;
232 }; 232 };
233 233
234 &cpu0 { 234 &cpu0 {
235 proc-supply = <&mt6397_vpca15_ 235 proc-supply = <&mt6397_vpca15_reg>;
236 }; 236 };
237 237
238 &cpu1 { 238 &cpu1 {
239 proc-supply = <&mt6397_vpca15_ 239 proc-supply = <&mt6397_vpca15_reg>;
240 }; 240 };
241 241
242 &cpu2 { 242 &cpu2 {
243 proc-supply = <&da9211_vcpu_re 243 proc-supply = <&da9211_vcpu_reg>;
244 sram-supply = <&mt6397_vsramca 244 sram-supply = <&mt6397_vsramca7_reg>;
245 }; 245 };
246 246
247 &cpu3 { 247 &cpu3 {
248 proc-supply = <&da9211_vcpu_re 248 proc-supply = <&da9211_vcpu_reg>;
249 sram-supply = <&mt6397_vsramca 249 sram-supply = <&mt6397_vsramca7_reg>;
250 }; 250 };
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