1 Binding for MediaTek's CPUFreq driver
2 =====================================
3
4 Required properties:
5 - clocks: A list of phandle + clock-specifier
6 - clock-names: Should contain the following:
7 "cpu" - The multiplexer for
8 "intermediate" - A parent of "cpu" cl
9 source (usually MAIN
10 transition and not s
11 Please refer to Documentation/devicetr
12 generic clock consumer properties.
13 - operating-points-v2: Please refer to Documen
14 for detail.
15 - proc-supply: Regulator for Vproc of CPU clus
16
17 Optional properties:
18 - sram-supply: Regulator for Vsram of CPU clus
19 needs to do "voltage tracking"
20 Vsram to fit SoC specific needs
21 flow is handled by hardware, he
22 needed.
23 - mediatek,cci:
24 Used to confirm the link status betwee
25 cpufreq and mediatek cci could share t
26 To prevent the issue of high frequency
27 property to make sure mediatek cci is
28 For details of mediatek cci, please re
29 Documentation/devicetree/bindings/inte
30 - #cooling-cells:
31 For details, please refer to
32 Documentation/devicetree/bindings/ther
33
34 Example 1 (MT7623 SoC):
35
36 cpu_opp_table: opp_table {
37 compatible = "operating-points
38 opp-shared;
39
40 opp-598000000 {
41 opp-hz = /bits/ 64 <59
42 opp-microvolt = <10500
43 };
44
45 opp-747500000 {
46 opp-hz = /bits/ 64 <74
47 opp-microvolt = <10500
48 };
49
50 opp-1040000000 {
51 opp-hz = /bits/ 64 <10
52 opp-microvolt = <11500
53 };
54
55 opp-1196000000 {
56 opp-hz = /bits/ 64 <11
57 opp-microvolt = <12000
58 };
59
60 opp-1300000000 {
61 opp-hz = /bits/ 64 <13
62 opp-microvolt = <13000
63 };
64 };
65
66 cpu0: cpu@0 {
67 device_type = "cpu";
68 compatible = "arm,cortex-a7";
69 reg = <0x0>;
70 clocks = <&infracfg CLK_INFRA_
71 <&apmixedsys CLK_APMI
72 clock-names = "cpu", "intermed
73 operating-points-v2 = <&cpu_op
74 #cooling-cells = <2>;
75 };
76 cpu@1 {
77 device_type = "cpu";
78 compatible = "arm,cortex-a7";
79 reg = <0x1>;
80 operating-points-v2 = <&cpu_op
81 };
82 cpu@2 {
83 device_type = "cpu";
84 compatible = "arm,cortex-a7";
85 reg = <0x2>;
86 operating-points-v2 = <&cpu_op
87 };
88 cpu@3 {
89 device_type = "cpu";
90 compatible = "arm,cortex-a7";
91 reg = <0x3>;
92 operating-points-v2 = <&cpu_op
93 };
94
95 Example 2 (MT8173 SoC):
96 cpu_opp_table_a: opp_table_a {
97 compatible = "operating-points
98 opp-shared;
99
100 opp-507000000 {
101 opp-hz = /bits/ 64 <50
102 opp-microvolt = <85900
103 };
104
105 opp-702000000 {
106 opp-hz = /bits/ 64 <70
107 opp-microvolt = <90800
108 };
109
110 opp-1001000000 {
111 opp-hz = /bits/ 64 <10
112 opp-microvolt = <98300
113 };
114
115 opp-1105000000 {
116 opp-hz = /bits/ 64 <11
117 opp-microvolt = <10090
118 };
119
120 opp-1183000000 {
121 opp-hz = /bits/ 64 <11
122 opp-microvolt = <10280
123 };
124
125 opp-1404000000 {
126 opp-hz = /bits/ 64 <14
127 opp-microvolt = <10830
128 };
129
130 opp-1508000000 {
131 opp-hz = /bits/ 64 <15
132 opp-microvolt = <11090
133 };
134
135 opp-1573000000 {
136 opp-hz = /bits/ 64 <15
137 opp-microvolt = <11250
138 };
139 };
140
141 cpu_opp_table_b: opp_table_b {
142 compatible = "operating-points
143 opp-shared;
144
145 opp-507000000 {
146 opp-hz = /bits/ 64 <50
147 opp-microvolt = <82800
148 };
149
150 opp-702000000 {
151 opp-hz = /bits/ 64 <70
152 opp-microvolt = <86700
153 };
154
155 opp-1001000000 {
156 opp-hz = /bits/ 64 <10
157 opp-microvolt = <92700
158 };
159
160 opp-1209000000 {
161 opp-hz = /bits/ 64 <12
162 opp-microvolt = <96800
163 };
164
165 opp-1404000000 {
166 opp-hz = /bits/ 64 <10
167 opp-microvolt = <10280
168 };
169
170 opp-1612000000 {
171 opp-hz = /bits/ 64 <16
172 opp-microvolt = <10490
173 };
174
175 opp-1807000000 {
176 opp-hz = /bits/ 64 <18
177 opp-microvolt = <10890
178 };
179
180 opp-1989000000 {
181 opp-hz = /bits/ 64 <19
182 opp-microvolt = <11250
183 };
184 };
185
186 cpu0: cpu@0 {
187 device_type = "cpu";
188 compatible = "arm,cortex-a53";
189 reg = <0x000>;
190 enable-method = "psci";
191 cpu-idle-states = <&CPU_SLEEP_
192 clocks = <&infracfg CLK_INFRA_
193 <&apmixedsys CLK_APMI
194 clock-names = "cpu", "intermed
195 operating-points-v2 = <&cpu_op
196 };
197
198 cpu1: cpu@1 {
199 device_type = "cpu";
200 compatible = "arm,cortex-a53";
201 reg = <0x001>;
202 enable-method = "psci";
203 cpu-idle-states = <&CPU_SLEEP_
204 clocks = <&infracfg CLK_INFRA_
205 <&apmixedsys CLK_APMI
206 clock-names = "cpu", "intermed
207 operating-points-v2 = <&cpu_op
208 };
209
210 cpu2: cpu@100 {
211 device_type = "cpu";
212 compatible = "arm,cortex-a72";
213 reg = <0x100>;
214 enable-method = "psci";
215 cpu-idle-states = <&CPU_SLEEP_
216 clocks = <&infracfg CLK_INFRA_
217 <&apmixedsys CLK_APMI
218 clock-names = "cpu", "intermed
219 operating-points-v2 = <&cpu_op
220 };
221
222 cpu3: cpu@101 {
223 device_type = "cpu";
224 compatible = "arm,cortex-a72";
225 reg = <0x101>;
226 enable-method = "psci";
227 cpu-idle-states = <&CPU_SLEEP_
228 clocks = <&infracfg CLK_INFRA_
229 <&apmixedsys CLK_APMI
230 clock-names = "cpu", "intermed
231 operating-points-v2 = <&cpu_op
232 };
233
234 &cpu0 {
235 proc-supply = <&mt6397_vpca15_
236 };
237
238 &cpu1 {
239 proc-supply = <&mt6397_vpca15_
240 };
241
242 &cpu2 {
243 proc-supply = <&da9211_vcpu_re
244 sram-supply = <&mt6397_vsramca
245 };
246
247 &cpu3 {
248 proc-supply = <&da9211_vcpu_re
249 sram-supply = <&mt6397_vsramca
250 };
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