1 Binding for MediaTek's CPUFreq driver 1 Binding for MediaTek's CPUFreq driver
2 ===================================== 2 =====================================
3 3
4 Required properties: 4 Required properties:
5 - clocks: A list of phandle + clock-specifier 5 - clocks: A list of phandle + clock-specifier pairs for the clocks listed in clock names.
6 - clock-names: Should contain the following: 6 - clock-names: Should contain the following:
7 "cpu" - The multiplexer for 7 "cpu" - The multiplexer for clock input of CPU cluster.
8 "intermediate" - A parent of "cpu" cl 8 "intermediate" - A parent of "cpu" clock which is used as "intermediate" clock
9 source (usually MAIN 9 source (usually MAINPLL) when the original CPU PLL is under
10 transition and not s 10 transition and not stable yet.
11 Please refer to Documentation/devicetr !! 11 Please refer to Documentation/devicetree/bindings/clk/clock-bindings.txt for
12 generic clock consumer properties. 12 generic clock consumer properties.
13 - operating-points-v2: Please refer to Documen !! 13 - operating-points-v2: Please refer to Documentation/devicetree/bindings/opp/opp.txt
14 for detail. 14 for detail.
15 - proc-supply: Regulator for Vproc of CPU clus 15 - proc-supply: Regulator for Vproc of CPU cluster.
16 16
17 Optional properties: 17 Optional properties:
18 - sram-supply: Regulator for Vsram of CPU clus 18 - sram-supply: Regulator for Vsram of CPU cluster. When present, the cpufreq driver
19 needs to do "voltage tracking" 19 needs to do "voltage tracking" to step by step scale up/down Vproc and
20 Vsram to fit SoC specific needs 20 Vsram to fit SoC specific needs. When absent, the voltage scaling
21 flow is handled by hardware, he 21 flow is handled by hardware, hence no software "voltage tracking" is
22 needed. 22 needed.
23 - mediatek,cci: <<
24 Used to confirm the link status betwee <<
25 cpufreq and mediatek cci could share t <<
26 To prevent the issue of high frequency <<
27 property to make sure mediatek cci is <<
28 For details of mediatek cci, please re <<
29 Documentation/devicetree/bindings/inte <<
30 - #cooling-cells: 23 - #cooling-cells:
31 For details, please refer to !! 24 - cooling-min-level:
32 Documentation/devicetree/bindings/ther !! 25 - cooling-max-level:
>> 26 Please refer to Documentation/devicetree/bindings/thermal/thermal.txt
>> 27 for detail.
33 28
34 Example 1 (MT7623 SoC): 29 Example 1 (MT7623 SoC):
35 30
36 cpu_opp_table: opp_table { 31 cpu_opp_table: opp_table {
37 compatible = "operating-points 32 compatible = "operating-points-v2";
38 opp-shared; 33 opp-shared;
39 34
40 opp-598000000 { 35 opp-598000000 {
41 opp-hz = /bits/ 64 <59 36 opp-hz = /bits/ 64 <598000000>;
42 opp-microvolt = <10500 37 opp-microvolt = <1050000>;
43 }; 38 };
44 39
45 opp-747500000 { 40 opp-747500000 {
46 opp-hz = /bits/ 64 <74 41 opp-hz = /bits/ 64 <747500000>;
47 opp-microvolt = <10500 42 opp-microvolt = <1050000>;
48 }; 43 };
49 44
50 opp-1040000000 { 45 opp-1040000000 {
51 opp-hz = /bits/ 64 <10 46 opp-hz = /bits/ 64 <1040000000>;
52 opp-microvolt = <11500 47 opp-microvolt = <1150000>;
53 }; 48 };
54 49
55 opp-1196000000 { 50 opp-1196000000 {
56 opp-hz = /bits/ 64 <11 51 opp-hz = /bits/ 64 <1196000000>;
57 opp-microvolt = <12000 52 opp-microvolt = <1200000>;
58 }; 53 };
59 54
60 opp-1300000000 { 55 opp-1300000000 {
61 opp-hz = /bits/ 64 <13 56 opp-hz = /bits/ 64 <1300000000>;
62 opp-microvolt = <13000 57 opp-microvolt = <1300000>;
63 }; 58 };
64 }; 59 };
65 60
66 cpu0: cpu@0 { 61 cpu0: cpu@0 {
67 device_type = "cpu"; 62 device_type = "cpu";
68 compatible = "arm,cortex-a7"; 63 compatible = "arm,cortex-a7";
69 reg = <0x0>; 64 reg = <0x0>;
70 clocks = <&infracfg CLK_INFRA_ 65 clocks = <&infracfg CLK_INFRA_CPUSEL>,
71 <&apmixedsys CLK_APMI 66 <&apmixedsys CLK_APMIXED_MAINPLL>;
72 clock-names = "cpu", "intermed 67 clock-names = "cpu", "intermediate";
73 operating-points-v2 = <&cpu_op 68 operating-points-v2 = <&cpu_opp_table>;
74 #cooling-cells = <2>; 69 #cooling-cells = <2>;
>> 70 cooling-min-level = <0>;
>> 71 cooling-max-level = <7>;
75 }; 72 };
76 cpu@1 { 73 cpu@1 {
77 device_type = "cpu"; 74 device_type = "cpu";
78 compatible = "arm,cortex-a7"; 75 compatible = "arm,cortex-a7";
79 reg = <0x1>; 76 reg = <0x1>;
80 operating-points-v2 = <&cpu_op 77 operating-points-v2 = <&cpu_opp_table>;
81 }; 78 };
82 cpu@2 { 79 cpu@2 {
83 device_type = "cpu"; 80 device_type = "cpu";
84 compatible = "arm,cortex-a7"; 81 compatible = "arm,cortex-a7";
85 reg = <0x2>; 82 reg = <0x2>;
86 operating-points-v2 = <&cpu_op 83 operating-points-v2 = <&cpu_opp_table>;
87 }; 84 };
88 cpu@3 { 85 cpu@3 {
89 device_type = "cpu"; 86 device_type = "cpu";
90 compatible = "arm,cortex-a7"; 87 compatible = "arm,cortex-a7";
91 reg = <0x3>; 88 reg = <0x3>;
92 operating-points-v2 = <&cpu_op 89 operating-points-v2 = <&cpu_opp_table>;
93 }; 90 };
94 91
95 Example 2 (MT8173 SoC): 92 Example 2 (MT8173 SoC):
96 cpu_opp_table_a: opp_table_a { 93 cpu_opp_table_a: opp_table_a {
97 compatible = "operating-points 94 compatible = "operating-points-v2";
98 opp-shared; 95 opp-shared;
99 96
100 opp-507000000 { 97 opp-507000000 {
101 opp-hz = /bits/ 64 <50 98 opp-hz = /bits/ 64 <507000000>;
102 opp-microvolt = <85900 99 opp-microvolt = <859000>;
103 }; 100 };
104 101
105 opp-702000000 { 102 opp-702000000 {
106 opp-hz = /bits/ 64 <70 103 opp-hz = /bits/ 64 <702000000>;
107 opp-microvolt = <90800 104 opp-microvolt = <908000>;
108 }; 105 };
109 106
110 opp-1001000000 { 107 opp-1001000000 {
111 opp-hz = /bits/ 64 <10 108 opp-hz = /bits/ 64 <1001000000>;
112 opp-microvolt = <98300 109 opp-microvolt = <983000>;
113 }; 110 };
114 111
115 opp-1105000000 { 112 opp-1105000000 {
116 opp-hz = /bits/ 64 <11 113 opp-hz = /bits/ 64 <1105000000>;
117 opp-microvolt = <10090 114 opp-microvolt = <1009000>;
118 }; 115 };
119 116
120 opp-1183000000 { 117 opp-1183000000 {
121 opp-hz = /bits/ 64 <11 118 opp-hz = /bits/ 64 <1183000000>;
122 opp-microvolt = <10280 119 opp-microvolt = <1028000>;
123 }; 120 };
124 121
125 opp-1404000000 { 122 opp-1404000000 {
126 opp-hz = /bits/ 64 <14 123 opp-hz = /bits/ 64 <1404000000>;
127 opp-microvolt = <10830 124 opp-microvolt = <1083000>;
128 }; 125 };
129 126
130 opp-1508000000 { 127 opp-1508000000 {
131 opp-hz = /bits/ 64 <15 128 opp-hz = /bits/ 64 <1508000000>;
132 opp-microvolt = <11090 129 opp-microvolt = <1109000>;
133 }; 130 };
134 131
135 opp-1573000000 { 132 opp-1573000000 {
136 opp-hz = /bits/ 64 <15 133 opp-hz = /bits/ 64 <1573000000>;
137 opp-microvolt = <11250 134 opp-microvolt = <1125000>;
138 }; 135 };
139 }; 136 };
140 137
141 cpu_opp_table_b: opp_table_b { 138 cpu_opp_table_b: opp_table_b {
142 compatible = "operating-points 139 compatible = "operating-points-v2";
143 opp-shared; 140 opp-shared;
144 141
145 opp-507000000 { 142 opp-507000000 {
146 opp-hz = /bits/ 64 <50 143 opp-hz = /bits/ 64 <507000000>;
147 opp-microvolt = <82800 144 opp-microvolt = <828000>;
148 }; 145 };
149 146
150 opp-702000000 { 147 opp-702000000 {
151 opp-hz = /bits/ 64 <70 148 opp-hz = /bits/ 64 <702000000>;
152 opp-microvolt = <86700 149 opp-microvolt = <867000>;
153 }; 150 };
154 151
155 opp-1001000000 { 152 opp-1001000000 {
156 opp-hz = /bits/ 64 <10 153 opp-hz = /bits/ 64 <1001000000>;
157 opp-microvolt = <92700 154 opp-microvolt = <927000>;
158 }; 155 };
159 156
160 opp-1209000000 { 157 opp-1209000000 {
161 opp-hz = /bits/ 64 <12 158 opp-hz = /bits/ 64 <1209000000>;
162 opp-microvolt = <96800 159 opp-microvolt = <968000>;
163 }; 160 };
164 161
165 opp-1404000000 { 162 opp-1404000000 {
166 opp-hz = /bits/ 64 <10 163 opp-hz = /bits/ 64 <1007000000>;
167 opp-microvolt = <10280 164 opp-microvolt = <1028000>;
168 }; 165 };
169 166
170 opp-1612000000 { 167 opp-1612000000 {
171 opp-hz = /bits/ 64 <16 168 opp-hz = /bits/ 64 <1612000000>;
172 opp-microvolt = <10490 169 opp-microvolt = <1049000>;
173 }; 170 };
174 171
175 opp-1807000000 { 172 opp-1807000000 {
176 opp-hz = /bits/ 64 <18 173 opp-hz = /bits/ 64 <1807000000>;
177 opp-microvolt = <10890 174 opp-microvolt = <1089000>;
178 }; 175 };
179 176
180 opp-1989000000 { 177 opp-1989000000 {
181 opp-hz = /bits/ 64 <19 178 opp-hz = /bits/ 64 <1989000000>;
182 opp-microvolt = <11250 179 opp-microvolt = <1125000>;
183 }; 180 };
184 }; 181 };
185 182
186 cpu0: cpu@0 { 183 cpu0: cpu@0 {
187 device_type = "cpu"; 184 device_type = "cpu";
188 compatible = "arm,cortex-a53"; 185 compatible = "arm,cortex-a53";
189 reg = <0x000>; 186 reg = <0x000>;
190 enable-method = "psci"; 187 enable-method = "psci";
191 cpu-idle-states = <&CPU_SLEEP_ 188 cpu-idle-states = <&CPU_SLEEP_0>;
192 clocks = <&infracfg CLK_INFRA_ 189 clocks = <&infracfg CLK_INFRA_CA53SEL>,
193 <&apmixedsys CLK_APMI 190 <&apmixedsys CLK_APMIXED_MAINPLL>;
194 clock-names = "cpu", "intermed 191 clock-names = "cpu", "intermediate";
195 operating-points-v2 = <&cpu_op 192 operating-points-v2 = <&cpu_opp_table_a>;
196 }; 193 };
197 194
198 cpu1: cpu@1 { 195 cpu1: cpu@1 {
199 device_type = "cpu"; 196 device_type = "cpu";
200 compatible = "arm,cortex-a53"; 197 compatible = "arm,cortex-a53";
201 reg = <0x001>; 198 reg = <0x001>;
202 enable-method = "psci"; 199 enable-method = "psci";
203 cpu-idle-states = <&CPU_SLEEP_ 200 cpu-idle-states = <&CPU_SLEEP_0>;
204 clocks = <&infracfg CLK_INFRA_ 201 clocks = <&infracfg CLK_INFRA_CA53SEL>,
205 <&apmixedsys CLK_APMI 202 <&apmixedsys CLK_APMIXED_MAINPLL>;
206 clock-names = "cpu", "intermed 203 clock-names = "cpu", "intermediate";
207 operating-points-v2 = <&cpu_op 204 operating-points-v2 = <&cpu_opp_table_a>;
208 }; 205 };
209 206
210 cpu2: cpu@100 { 207 cpu2: cpu@100 {
211 device_type = "cpu"; 208 device_type = "cpu";
212 compatible = "arm,cortex-a72"; !! 209 compatible = "arm,cortex-a57";
213 reg = <0x100>; 210 reg = <0x100>;
214 enable-method = "psci"; 211 enable-method = "psci";
215 cpu-idle-states = <&CPU_SLEEP_ 212 cpu-idle-states = <&CPU_SLEEP_0>;
216 clocks = <&infracfg CLK_INFRA_ !! 213 clocks = <&infracfg CLK_INFRA_CA57SEL>,
217 <&apmixedsys CLK_APMI 214 <&apmixedsys CLK_APMIXED_MAINPLL>;
218 clock-names = "cpu", "intermed 215 clock-names = "cpu", "intermediate";
219 operating-points-v2 = <&cpu_op 216 operating-points-v2 = <&cpu_opp_table_b>;
220 }; 217 };
221 218
222 cpu3: cpu@101 { 219 cpu3: cpu@101 {
223 device_type = "cpu"; 220 device_type = "cpu";
224 compatible = "arm,cortex-a72"; !! 221 compatible = "arm,cortex-a57";
225 reg = <0x101>; 222 reg = <0x101>;
226 enable-method = "psci"; 223 enable-method = "psci";
227 cpu-idle-states = <&CPU_SLEEP_ 224 cpu-idle-states = <&CPU_SLEEP_0>;
228 clocks = <&infracfg CLK_INFRA_ !! 225 clocks = <&infracfg CLK_INFRA_CA57SEL>,
229 <&apmixedsys CLK_APMI 226 <&apmixedsys CLK_APMIXED_MAINPLL>;
230 clock-names = "cpu", "intermed 227 clock-names = "cpu", "intermediate";
231 operating-points-v2 = <&cpu_op 228 operating-points-v2 = <&cpu_opp_table_b>;
232 }; 229 };
233 230
234 &cpu0 { 231 &cpu0 {
235 proc-supply = <&mt6397_vpca15_ 232 proc-supply = <&mt6397_vpca15_reg>;
236 }; 233 };
237 234
238 &cpu1 { 235 &cpu1 {
239 proc-supply = <&mt6397_vpca15_ 236 proc-supply = <&mt6397_vpca15_reg>;
240 }; 237 };
241 238
242 &cpu2 { 239 &cpu2 {
243 proc-supply = <&da9211_vcpu_re 240 proc-supply = <&da9211_vcpu_reg>;
244 sram-supply = <&mt6397_vsramca 241 sram-supply = <&mt6397_vsramca7_reg>;
245 }; 242 };
246 243
247 &cpu3 { 244 &cpu3 {
248 proc-supply = <&da9211_vcpu_re 245 proc-supply = <&da9211_vcpu_reg>;
249 sram-supply = <&mt6397_vsramca 246 sram-supply = <&mt6397_vsramca7_reg>;
250 }; 247 };
Linux® is a registered trademark of Linus Torvalds in the United States and other countries.
TOMOYO® is a registered trademark of NTT DATA CORPORATION.