1 Binding for MediaTek's CPUFreq driver 1 Binding for MediaTek's CPUFreq driver
2 ===================================== 2 =====================================
3 3
4 Required properties: 4 Required properties:
5 - clocks: A list of phandle + clock-specifier 5 - clocks: A list of phandle + clock-specifier pairs for the clocks listed in clock names.
6 - clock-names: Should contain the following: 6 - clock-names: Should contain the following:
7 "cpu" - The multiplexer for 7 "cpu" - The multiplexer for clock input of CPU cluster.
8 "intermediate" - A parent of "cpu" cl 8 "intermediate" - A parent of "cpu" clock which is used as "intermediate" clock
9 source (usually MAIN 9 source (usually MAINPLL) when the original CPU PLL is under
10 transition and not s 10 transition and not stable yet.
11 Please refer to Documentation/devicetr 11 Please refer to Documentation/devicetree/bindings/clock/clock-bindings.txt for
12 generic clock consumer properties. 12 generic clock consumer properties.
13 - operating-points-v2: Please refer to Documen !! 13 - operating-points-v2: Please refer to Documentation/devicetree/bindings/opp/opp.txt
14 for detail. 14 for detail.
15 - proc-supply: Regulator for Vproc of CPU clus 15 - proc-supply: Regulator for Vproc of CPU cluster.
16 16
17 Optional properties: 17 Optional properties:
18 - sram-supply: Regulator for Vsram of CPU clus 18 - sram-supply: Regulator for Vsram of CPU cluster. When present, the cpufreq driver
19 needs to do "voltage tracking" 19 needs to do "voltage tracking" to step by step scale up/down Vproc and
20 Vsram to fit SoC specific needs 20 Vsram to fit SoC specific needs. When absent, the voltage scaling
21 flow is handled by hardware, he 21 flow is handled by hardware, hence no software "voltage tracking" is
22 needed. 22 needed.
23 - mediatek,cci: <<
24 Used to confirm the link status betwee <<
25 cpufreq and mediatek cci could share t <<
26 To prevent the issue of high frequency <<
27 property to make sure mediatek cci is <<
28 For details of mediatek cci, please re <<
29 Documentation/devicetree/bindings/inte <<
30 - #cooling-cells: 23 - #cooling-cells:
31 For details, please refer to 24 For details, please refer to
32 Documentation/devicetree/bindings/ther 25 Documentation/devicetree/bindings/thermal/thermal-cooling-devices.yaml
33 26
34 Example 1 (MT7623 SoC): 27 Example 1 (MT7623 SoC):
35 28
36 cpu_opp_table: opp_table { 29 cpu_opp_table: opp_table {
37 compatible = "operating-points 30 compatible = "operating-points-v2";
38 opp-shared; 31 opp-shared;
39 32
40 opp-598000000 { 33 opp-598000000 {
41 opp-hz = /bits/ 64 <59 34 opp-hz = /bits/ 64 <598000000>;
42 opp-microvolt = <10500 35 opp-microvolt = <1050000>;
43 }; 36 };
44 37
45 opp-747500000 { 38 opp-747500000 {
46 opp-hz = /bits/ 64 <74 39 opp-hz = /bits/ 64 <747500000>;
47 opp-microvolt = <10500 40 opp-microvolt = <1050000>;
48 }; 41 };
49 42
50 opp-1040000000 { 43 opp-1040000000 {
51 opp-hz = /bits/ 64 <10 44 opp-hz = /bits/ 64 <1040000000>;
52 opp-microvolt = <11500 45 opp-microvolt = <1150000>;
53 }; 46 };
54 47
55 opp-1196000000 { 48 opp-1196000000 {
56 opp-hz = /bits/ 64 <11 49 opp-hz = /bits/ 64 <1196000000>;
57 opp-microvolt = <12000 50 opp-microvolt = <1200000>;
58 }; 51 };
59 52
60 opp-1300000000 { 53 opp-1300000000 {
61 opp-hz = /bits/ 64 <13 54 opp-hz = /bits/ 64 <1300000000>;
62 opp-microvolt = <13000 55 opp-microvolt = <1300000>;
63 }; 56 };
64 }; 57 };
65 58
66 cpu0: cpu@0 { 59 cpu0: cpu@0 {
67 device_type = "cpu"; 60 device_type = "cpu";
68 compatible = "arm,cortex-a7"; 61 compatible = "arm,cortex-a7";
69 reg = <0x0>; 62 reg = <0x0>;
70 clocks = <&infracfg CLK_INFRA_ 63 clocks = <&infracfg CLK_INFRA_CPUSEL>,
71 <&apmixedsys CLK_APMI 64 <&apmixedsys CLK_APMIXED_MAINPLL>;
72 clock-names = "cpu", "intermed 65 clock-names = "cpu", "intermediate";
73 operating-points-v2 = <&cpu_op 66 operating-points-v2 = <&cpu_opp_table>;
74 #cooling-cells = <2>; 67 #cooling-cells = <2>;
75 }; 68 };
76 cpu@1 { 69 cpu@1 {
77 device_type = "cpu"; 70 device_type = "cpu";
78 compatible = "arm,cortex-a7"; 71 compatible = "arm,cortex-a7";
79 reg = <0x1>; 72 reg = <0x1>;
80 operating-points-v2 = <&cpu_op 73 operating-points-v2 = <&cpu_opp_table>;
81 }; 74 };
82 cpu@2 { 75 cpu@2 {
83 device_type = "cpu"; 76 device_type = "cpu";
84 compatible = "arm,cortex-a7"; 77 compatible = "arm,cortex-a7";
85 reg = <0x2>; 78 reg = <0x2>;
86 operating-points-v2 = <&cpu_op 79 operating-points-v2 = <&cpu_opp_table>;
87 }; 80 };
88 cpu@3 { 81 cpu@3 {
89 device_type = "cpu"; 82 device_type = "cpu";
90 compatible = "arm,cortex-a7"; 83 compatible = "arm,cortex-a7";
91 reg = <0x3>; 84 reg = <0x3>;
92 operating-points-v2 = <&cpu_op 85 operating-points-v2 = <&cpu_opp_table>;
93 }; 86 };
94 87
95 Example 2 (MT8173 SoC): 88 Example 2 (MT8173 SoC):
96 cpu_opp_table_a: opp_table_a { 89 cpu_opp_table_a: opp_table_a {
97 compatible = "operating-points 90 compatible = "operating-points-v2";
98 opp-shared; 91 opp-shared;
99 92
100 opp-507000000 { 93 opp-507000000 {
101 opp-hz = /bits/ 64 <50 94 opp-hz = /bits/ 64 <507000000>;
102 opp-microvolt = <85900 95 opp-microvolt = <859000>;
103 }; 96 };
104 97
105 opp-702000000 { 98 opp-702000000 {
106 opp-hz = /bits/ 64 <70 99 opp-hz = /bits/ 64 <702000000>;
107 opp-microvolt = <90800 100 opp-microvolt = <908000>;
108 }; 101 };
109 102
110 opp-1001000000 { 103 opp-1001000000 {
111 opp-hz = /bits/ 64 <10 104 opp-hz = /bits/ 64 <1001000000>;
112 opp-microvolt = <98300 105 opp-microvolt = <983000>;
113 }; 106 };
114 107
115 opp-1105000000 { 108 opp-1105000000 {
116 opp-hz = /bits/ 64 <11 109 opp-hz = /bits/ 64 <1105000000>;
117 opp-microvolt = <10090 110 opp-microvolt = <1009000>;
118 }; 111 };
119 112
120 opp-1183000000 { 113 opp-1183000000 {
121 opp-hz = /bits/ 64 <11 114 opp-hz = /bits/ 64 <1183000000>;
122 opp-microvolt = <10280 115 opp-microvolt = <1028000>;
123 }; 116 };
124 117
125 opp-1404000000 { 118 opp-1404000000 {
126 opp-hz = /bits/ 64 <14 119 opp-hz = /bits/ 64 <1404000000>;
127 opp-microvolt = <10830 120 opp-microvolt = <1083000>;
128 }; 121 };
129 122
130 opp-1508000000 { 123 opp-1508000000 {
131 opp-hz = /bits/ 64 <15 124 opp-hz = /bits/ 64 <1508000000>;
132 opp-microvolt = <11090 125 opp-microvolt = <1109000>;
133 }; 126 };
134 127
135 opp-1573000000 { 128 opp-1573000000 {
136 opp-hz = /bits/ 64 <15 129 opp-hz = /bits/ 64 <1573000000>;
137 opp-microvolt = <11250 130 opp-microvolt = <1125000>;
138 }; 131 };
139 }; 132 };
140 133
141 cpu_opp_table_b: opp_table_b { 134 cpu_opp_table_b: opp_table_b {
142 compatible = "operating-points 135 compatible = "operating-points-v2";
143 opp-shared; 136 opp-shared;
144 137
145 opp-507000000 { 138 opp-507000000 {
146 opp-hz = /bits/ 64 <50 139 opp-hz = /bits/ 64 <507000000>;
147 opp-microvolt = <82800 140 opp-microvolt = <828000>;
148 }; 141 };
149 142
150 opp-702000000 { 143 opp-702000000 {
151 opp-hz = /bits/ 64 <70 144 opp-hz = /bits/ 64 <702000000>;
152 opp-microvolt = <86700 145 opp-microvolt = <867000>;
153 }; 146 };
154 147
155 opp-1001000000 { 148 opp-1001000000 {
156 opp-hz = /bits/ 64 <10 149 opp-hz = /bits/ 64 <1001000000>;
157 opp-microvolt = <92700 150 opp-microvolt = <927000>;
158 }; 151 };
159 152
160 opp-1209000000 { 153 opp-1209000000 {
161 opp-hz = /bits/ 64 <12 154 opp-hz = /bits/ 64 <1209000000>;
162 opp-microvolt = <96800 155 opp-microvolt = <968000>;
163 }; 156 };
164 157
165 opp-1404000000 { 158 opp-1404000000 {
166 opp-hz = /bits/ 64 <10 159 opp-hz = /bits/ 64 <1007000000>;
167 opp-microvolt = <10280 160 opp-microvolt = <1028000>;
168 }; 161 };
169 162
170 opp-1612000000 { 163 opp-1612000000 {
171 opp-hz = /bits/ 64 <16 164 opp-hz = /bits/ 64 <1612000000>;
172 opp-microvolt = <10490 165 opp-microvolt = <1049000>;
173 }; 166 };
174 167
175 opp-1807000000 { 168 opp-1807000000 {
176 opp-hz = /bits/ 64 <18 169 opp-hz = /bits/ 64 <1807000000>;
177 opp-microvolt = <10890 170 opp-microvolt = <1089000>;
178 }; 171 };
179 172
180 opp-1989000000 { 173 opp-1989000000 {
181 opp-hz = /bits/ 64 <19 174 opp-hz = /bits/ 64 <1989000000>;
182 opp-microvolt = <11250 175 opp-microvolt = <1125000>;
183 }; 176 };
184 }; 177 };
185 178
186 cpu0: cpu@0 { 179 cpu0: cpu@0 {
187 device_type = "cpu"; 180 device_type = "cpu";
188 compatible = "arm,cortex-a53"; 181 compatible = "arm,cortex-a53";
189 reg = <0x000>; 182 reg = <0x000>;
190 enable-method = "psci"; 183 enable-method = "psci";
191 cpu-idle-states = <&CPU_SLEEP_ 184 cpu-idle-states = <&CPU_SLEEP_0>;
192 clocks = <&infracfg CLK_INFRA_ 185 clocks = <&infracfg CLK_INFRA_CA53SEL>,
193 <&apmixedsys CLK_APMI 186 <&apmixedsys CLK_APMIXED_MAINPLL>;
194 clock-names = "cpu", "intermed 187 clock-names = "cpu", "intermediate";
195 operating-points-v2 = <&cpu_op 188 operating-points-v2 = <&cpu_opp_table_a>;
196 }; 189 };
197 190
198 cpu1: cpu@1 { 191 cpu1: cpu@1 {
199 device_type = "cpu"; 192 device_type = "cpu";
200 compatible = "arm,cortex-a53"; 193 compatible = "arm,cortex-a53";
201 reg = <0x001>; 194 reg = <0x001>;
202 enable-method = "psci"; 195 enable-method = "psci";
203 cpu-idle-states = <&CPU_SLEEP_ 196 cpu-idle-states = <&CPU_SLEEP_0>;
204 clocks = <&infracfg CLK_INFRA_ 197 clocks = <&infracfg CLK_INFRA_CA53SEL>,
205 <&apmixedsys CLK_APMI 198 <&apmixedsys CLK_APMIXED_MAINPLL>;
206 clock-names = "cpu", "intermed 199 clock-names = "cpu", "intermediate";
207 operating-points-v2 = <&cpu_op 200 operating-points-v2 = <&cpu_opp_table_a>;
208 }; 201 };
209 202
210 cpu2: cpu@100 { 203 cpu2: cpu@100 {
211 device_type = "cpu"; 204 device_type = "cpu";
212 compatible = "arm,cortex-a72"; !! 205 compatible = "arm,cortex-a57";
213 reg = <0x100>; 206 reg = <0x100>;
214 enable-method = "psci"; 207 enable-method = "psci";
215 cpu-idle-states = <&CPU_SLEEP_ 208 cpu-idle-states = <&CPU_SLEEP_0>;
216 clocks = <&infracfg CLK_INFRA_ !! 209 clocks = <&infracfg CLK_INFRA_CA57SEL>,
217 <&apmixedsys CLK_APMI 210 <&apmixedsys CLK_APMIXED_MAINPLL>;
218 clock-names = "cpu", "intermed 211 clock-names = "cpu", "intermediate";
219 operating-points-v2 = <&cpu_op 212 operating-points-v2 = <&cpu_opp_table_b>;
220 }; 213 };
221 214
222 cpu3: cpu@101 { 215 cpu3: cpu@101 {
223 device_type = "cpu"; 216 device_type = "cpu";
224 compatible = "arm,cortex-a72"; !! 217 compatible = "arm,cortex-a57";
225 reg = <0x101>; 218 reg = <0x101>;
226 enable-method = "psci"; 219 enable-method = "psci";
227 cpu-idle-states = <&CPU_SLEEP_ 220 cpu-idle-states = <&CPU_SLEEP_0>;
228 clocks = <&infracfg CLK_INFRA_ !! 221 clocks = <&infracfg CLK_INFRA_CA57SEL>,
229 <&apmixedsys CLK_APMI 222 <&apmixedsys CLK_APMIXED_MAINPLL>;
230 clock-names = "cpu", "intermed 223 clock-names = "cpu", "intermediate";
231 operating-points-v2 = <&cpu_op 224 operating-points-v2 = <&cpu_opp_table_b>;
232 }; 225 };
233 226
234 &cpu0 { 227 &cpu0 {
235 proc-supply = <&mt6397_vpca15_ 228 proc-supply = <&mt6397_vpca15_reg>;
236 }; 229 };
237 230
238 &cpu1 { 231 &cpu1 {
239 proc-supply = <&mt6397_vpca15_ 232 proc-supply = <&mt6397_vpca15_reg>;
240 }; 233 };
241 234
242 &cpu2 { 235 &cpu2 {
243 proc-supply = <&da9211_vcpu_re 236 proc-supply = <&da9211_vcpu_reg>;
244 sram-supply = <&mt6397_vsramca 237 sram-supply = <&mt6397_vsramca7_reg>;
245 }; 238 };
246 239
247 &cpu3 { 240 &cpu3 {
248 proc-supply = <&da9211_vcpu_re 241 proc-supply = <&da9211_vcpu_reg>;
249 sram-supply = <&mt6397_vsramca 242 sram-supply = <&mt6397_vsramca7_reg>;
250 }; 243 };
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