1 Tegra124 CPU frequency scaling driver bindings 1 Tegra124 CPU frequency scaling driver bindings
2 ---------------------------------------------- 2 ----------------------------------------------
3 3
4 Both required and optional properties listed b 4 Both required and optional properties listed below must be defined
5 under node /cpus/cpu@0. 5 under node /cpus/cpu@0.
6 6
7 Required properties: 7 Required properties:
8 - clocks: Must contain an entry for each entry 8 - clocks: Must contain an entry for each entry in clock-names.
9 See ../clocks/clock-bindings.txt for details 9 See ../clocks/clock-bindings.txt for details.
10 - clock-names: Must include the following entr 10 - clock-names: Must include the following entries:
11 - cpu_g: Clock mux for the fast CPU cluster. 11 - cpu_g: Clock mux for the fast CPU cluster.
>> 12 - cpu_lp: Clock mux for the low-power CPU cluster.
12 - pll_x: Fast PLL clocksource. 13 - pll_x: Fast PLL clocksource.
13 - pll_p: Auxiliary PLL used during fast PLL 14 - pll_p: Auxiliary PLL used during fast PLL rate changes.
14 - dfll: Fast DFLL clocksource that also auto 15 - dfll: Fast DFLL clocksource that also automatically scales CPU voltage.
>> 16 - vdd-cpu-supply: Regulator for CPU voltage
15 17
16 Optional properties: 18 Optional properties:
17 - clock-latency: Specify the possible maximum 19 - clock-latency: Specify the possible maximum transition latency for clock,
18 in unit of nanoseconds. 20 in unit of nanoseconds.
19 21
20 Example: 22 Example:
21 -------- 23 --------
22 cpus { 24 cpus {
23 #address-cells = <1>; 25 #address-cells = <1>;
24 #size-cells = <0>; 26 #size-cells = <0>;
25 27
26 cpu@0 { 28 cpu@0 {
27 device_type = "cpu"; 29 device_type = "cpu";
28 compatible = "arm,cortex-a15"; 30 compatible = "arm,cortex-a15";
29 reg = <0>; 31 reg = <0>;
30 32
31 clocks = <&tegra_car TEGRA124_ 33 clocks = <&tegra_car TEGRA124_CLK_CCLK_G>,
>> 34 <&tegra_car TEGRA124_CLK_CCLK_LP>,
32 <&tegra_car TEGRA124_ 35 <&tegra_car TEGRA124_CLK_PLL_X>,
33 <&tegra_car TEGRA124_ 36 <&tegra_car TEGRA124_CLK_PLL_P>,
34 <&dfll>; 37 <&dfll>;
35 clock-names = "cpu_g", "pll_x" !! 38 clock-names = "cpu_g", "cpu_lp", "pll_x", "pll_p", "dfll";
36 clock-latency = <300000>; 39 clock-latency = <300000>;
>> 40 vdd-cpu-supply: <&vdd_cpu>;
37 }; 41 };
38 42
39 <...> 43 <...>
40 }; 44 };
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