1 # SPDX-License-Identifier: (GPL-2.0-only OR BS 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 %YAML 1.2 2 %YAML 1.2
3 --- 3 ---
4 $id: http://devicetree.org/schemas/crypto/aspe 4 $id: http://devicetree.org/schemas/crypto/aspeed,ast2500-hace.yaml#
5 $schema: http://devicetree.org/meta-schemas/co 5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6 6
7 title: ASPEED HACE hash and crypto Hardware Ac 7 title: ASPEED HACE hash and crypto Hardware Accelerator Engines
8 8
9 maintainers: 9 maintainers:
10 - Neal Liu <neal_liu@aspeedtech.com> 10 - Neal Liu <neal_liu@aspeedtech.com>
11 11
12 description: | 12 description: |
13 The Hash and Crypto Engine (HACE) is designe 13 The Hash and Crypto Engine (HACE) is designed to accelerate the throughput
14 of hash data digest, encryption, and decrypt 14 of hash data digest, encryption, and decryption. Basically, HACE can be
15 divided into two independently engines - Has 15 divided into two independently engines - Hash Engine and Crypto Engine.
16 16
17 properties: 17 properties:
18 compatible: 18 compatible:
19 enum: 19 enum:
20 - aspeed,ast2500-hace 20 - aspeed,ast2500-hace
21 - aspeed,ast2600-hace 21 - aspeed,ast2600-hace
22 22
23 reg: 23 reg:
24 maxItems: 1 24 maxItems: 1
25 25
26 clocks: 26 clocks:
27 maxItems: 1 27 maxItems: 1
28 28
29 interrupts: 29 interrupts:
30 maxItems: 1 30 maxItems: 1
31 31
32 resets: 32 resets:
33 maxItems: 1 33 maxItems: 1
34 34
35 required: 35 required:
36 - compatible 36 - compatible
37 - reg 37 - reg
38 - clocks 38 - clocks
39 - interrupts 39 - interrupts
40 - resets 40 - resets
41 41
42 additionalProperties: false 42 additionalProperties: false
43 43
44 examples: 44 examples:
45 - | 45 - |
46 #include <dt-bindings/clock/ast2600-clock. 46 #include <dt-bindings/clock/ast2600-clock.h>
47 hace: crypto@1e6d0000 { 47 hace: crypto@1e6d0000 {
48 compatible = "aspeed,ast2600-hace"; 48 compatible = "aspeed,ast2600-hace";
49 reg = <0x1e6d0000 0x200>; 49 reg = <0x1e6d0000 0x200>;
50 interrupts = <4>; 50 interrupts = <4>;
51 clocks = <&syscon ASPEED_CLK_GATE_YCLK 51 clocks = <&syscon ASPEED_CLK_GATE_YCLK>;
52 resets = <&syscon ASPEED_RESET_HACE>; 52 resets = <&syscon ASPEED_RESET_HACE>;
53 }; 53 };
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