1 # SPDX-License-Identifier: (GPL-2.0-only OR BS 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2022 Microchip Technology, Inc 2 # Copyright (C) 2022 Microchip Technology, Inc. and its subsidiaries
3 %YAML 1.2 3 %YAML 1.2
4 --- 4 ---
5 $id: http://devicetree.org/schemas/crypto/atme 5 $id: http://devicetree.org/schemas/crypto/atmel,at91sam9g46-sha.yaml#
6 $schema: http://devicetree.org/meta-schemas/co 6 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 7
8 title: Atmel Secure Hash Algorithm (SHA) HW cr 8 title: Atmel Secure Hash Algorithm (SHA) HW cryptographic accelerator
9 9
10 maintainers: 10 maintainers:
11 - Tudor Ambarus <tudor.ambarus@linaro.org> 11 - Tudor Ambarus <tudor.ambarus@linaro.org>
12 12
13 properties: 13 properties:
14 compatible: 14 compatible:
15 oneOf: !! 15 const: atmel,at91sam9g46-sha
16 - const: atmel,at91sam9g46-sha <<
17 - items: <<
18 - const: microchip,sam9x7-sha <<
19 - const: atmel,at91sam9g46-sha <<
20 16
21 reg: 17 reg:
22 maxItems: 1 18 maxItems: 1
23 19
24 interrupts: 20 interrupts:
25 maxItems: 1 21 maxItems: 1
26 22
27 clocks: 23 clocks:
28 maxItems: 1 24 maxItems: 1
29 25
30 clock-names: 26 clock-names:
31 const: sha_clk 27 const: sha_clk
32 28
33 dmas: 29 dmas:
34 maxItems: 1 30 maxItems: 1
35 description: TX DMA Channel 31 description: TX DMA Channel
36 32
37 dma-names: 33 dma-names:
38 const: tx 34 const: tx
39 35
40 required: 36 required:
41 - compatible 37 - compatible
42 - reg 38 - reg
43 - interrupts 39 - interrupts
44 - clocks 40 - clocks
45 - clock-names 41 - clock-names
46 42
47 additionalProperties: false 43 additionalProperties: false
48 44
49 examples: 45 examples:
50 - | 46 - |
51 #include <dt-bindings/interrupt-controller 47 #include <dt-bindings/interrupt-controller/irq.h>
52 #include <dt-bindings/interrupt-controller 48 #include <dt-bindings/interrupt-controller/arm-gic.h>
53 #include <dt-bindings/clock/at91.h> 49 #include <dt-bindings/clock/at91.h>
54 #include <dt-bindings/dma/at91.h> 50 #include <dt-bindings/dma/at91.h>
55 51
56 sha: crypto@e1814000 { 52 sha: crypto@e1814000 {
57 compatible = "atmel,at91sam9g46-sha"; 53 compatible = "atmel,at91sam9g46-sha";
58 reg = <0xe1814000 0x100>; 54 reg = <0xe1814000 0x100>;
59 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_ 55 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
60 clocks = <&pmc PMC_TYPE_PERIPHERAL 83>; 56 clocks = <&pmc PMC_TYPE_PERIPHERAL 83>;
61 clock-names = "sha_clk"; 57 clock-names = "sha_clk";
62 dmas = <&dma0 AT91_XDMAC_DT_PERID(48)>; 58 dmas = <&dma0 AT91_XDMAC_DT_PERID(48)>;
63 dma-names = "tx"; 59 dma-names = "tx";
64 }; 60 };
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