1 # SPDX-License-Identifier: GPL-2.0 1 # SPDX-License-Identifier: GPL-2.0
2 %YAML 1.2 2 %YAML 1.2
3 --- 3 ---
4 $id: http://devicetree.org/schemas/display/all 4 $id: http://devicetree.org/schemas/display/allwinner,sun6i-a31-drc.yaml#
5 $schema: http://devicetree.org/meta-schemas/co 5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6 6
7 title: Allwinner A31 Dynamic Range Controller !! 7 title: Allwinner A31 Dynamic Range Controller Device Tree Bindings
8 8
9 maintainers: 9 maintainers:
10 - Chen-Yu Tsai <wens@csie.org> 10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org> 11 - Maxime Ripard <mripard@kernel.org>
12 12
13 description: | 13 description: |
14 The DRC (Dynamic Range Controller) allows to 14 The DRC (Dynamic Range Controller) allows to dynamically adjust
15 pixel brightness/contrast based on histogram 15 pixel brightness/contrast based on histogram measurements for LCD
16 content adaptive backlight control. 16 content adaptive backlight control.
17 17
18 properties: 18 properties:
19 compatible: 19 compatible:
20 enum: 20 enum:
21 - allwinner,sun6i-a31-drc 21 - allwinner,sun6i-a31-drc
22 - allwinner,sun6i-a31s-drc 22 - allwinner,sun6i-a31s-drc
23 - allwinner,sun8i-a23-drc 23 - allwinner,sun8i-a23-drc
24 - allwinner,sun8i-a33-drc 24 - allwinner,sun8i-a33-drc
25 - allwinner,sun9i-a80-drc 25 - allwinner,sun9i-a80-drc
26 26
27 reg: 27 reg:
28 maxItems: 1 28 maxItems: 1
29 29
30 interrupts: 30 interrupts:
31 maxItems: 1 31 maxItems: 1
32 32
33 clocks: 33 clocks:
34 items: 34 items:
35 - description: The DRC interface clock 35 - description: The DRC interface clock
36 - description: The DRC module clock 36 - description: The DRC module clock
37 - description: The DRC DRAM clock 37 - description: The DRC DRAM clock
38 38
39 clock-names: 39 clock-names:
40 items: 40 items:
41 - const: ahb 41 - const: ahb
42 - const: mod 42 - const: mod
43 - const: ram 43 - const: ram
44 44
45 resets: 45 resets:
46 maxItems: 1 46 maxItems: 1
47 47
48 ports: 48 ports:
49 $ref: /schemas/graph.yaml#/properties/port !! 49 type: object
>> 50 description: |
>> 51 A ports node with endpoint definitions as defined in
>> 52 Documentation/devicetree/bindings/media/video-interfaces.txt.
50 53
51 properties: 54 properties:
>> 55 "#address-cells":
>> 56 const: 1
>> 57
>> 58 "#size-cells":
>> 59 const: 0
>> 60
52 port@0: 61 port@0:
53 $ref: /schemas/graph.yaml#/properties/ !! 62 type: object
54 description: | 63 description: |
55 Input endpoints of the controller. 64 Input endpoints of the controller.
56 65
57 port@1: 66 port@1:
58 $ref: /schemas/graph.yaml#/properties/ !! 67 type: object
59 description: | 68 description: |
60 Output endpoints of the controller. 69 Output endpoints of the controller.
61 70
62 required: 71 required:
>> 72 - "#address-cells"
>> 73 - "#size-cells"
63 - port@0 74 - port@0
64 - port@1 75 - port@1
>> 76
>> 77 additionalProperties: false
65 78
66 required: 79 required:
67 - compatible 80 - compatible
68 - reg 81 - reg
69 - interrupts 82 - interrupts
70 - clocks 83 - clocks
71 - clock-names 84 - clock-names
72 - resets 85 - resets
73 - ports 86 - ports
74 87
75 additionalProperties: false 88 additionalProperties: false
76 89
77 examples: 90 examples:
78 - | 91 - |
79 #include <dt-bindings/interrupt-controller 92 #include <dt-bindings/interrupt-controller/arm-gic.h>
80 93
81 #include <dt-bindings/clock/sun6i-a31-ccu. 94 #include <dt-bindings/clock/sun6i-a31-ccu.h>
82 #include <dt-bindings/reset/sun6i-a31-ccu. 95 #include <dt-bindings/reset/sun6i-a31-ccu.h>
83 96
84 drc0: drc@1e70000 { 97 drc0: drc@1e70000 {
85 compatible = "allwinner,sun6i-a31-drc" 98 compatible = "allwinner,sun6i-a31-drc";
86 reg = <0x01e70000 0x10000>; 99 reg = <0x01e70000 0x10000>;
87 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVE 100 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
88 clocks = <&ccu CLK_AHB1_DRC0>, <&ccu C 101 clocks = <&ccu CLK_AHB1_DRC0>, <&ccu CLK_IEP_DRC0>,
89 <&ccu CLK_DRAM_DRC0>; 102 <&ccu CLK_DRAM_DRC0>;
90 clock-names = "ahb", "mod", 103 clock-names = "ahb", "mod",
91 "ram"; 104 "ram";
92 resets = <&ccu RST_AHB1_DRC0>; 105 resets = <&ccu RST_AHB1_DRC0>;
93 106
94 ports { 107 ports {
95 #address-cells = <1>; 108 #address-cells = <1>;
96 #size-cells = <0>; 109 #size-cells = <0>;
97 110
98 drc0_in: port@0 { 111 drc0_in: port@0 {
99 reg = <0>; 112 reg = <0>;
100 113
101 drc0_in_be0: endpoint { 114 drc0_in_be0: endpoint {
102 remote-endpoint = <&be0_ou 115 remote-endpoint = <&be0_out_drc0>;
103 }; 116 };
104 }; 117 };
105 118
106 drc0_out: port@1 { 119 drc0_out: port@1 {
107 #address-cells = <1>; 120 #address-cells = <1>;
108 #size-cells = <0>; 121 #size-cells = <0>;
109 reg = <1>; 122 reg = <1>;
110 123
111 drc0_out_tcon0: endpoint@0 { 124 drc0_out_tcon0: endpoint@0 {
112 reg = <0>; 125 reg = <0>;
113 remote-endpoint = <&tcon0_ 126 remote-endpoint = <&tcon0_in_drc0>;
114 }; 127 };
115 128
116 drc0_out_tcon1: endpoint@1 { 129 drc0_out_tcon1: endpoint@1 {
117 reg = <1>; 130 reg = <1>;
118 remote-endpoint = <&tcon1_ 131 remote-endpoint = <&tcon1_in_drc0>;
119 }; 132 };
120 }; 133 };
121 }; 134 };
122 }; 135 };
123 136
124 137
125 ... 138 ...
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