1 # SPDX-License-Identifier: (GPL-2.0-only OR BS 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 %YAML 1.2 2 %YAML 1.2
3 --- 3 ---
4 $id: http://devicetree.org/schemas/display/bri 4 $id: http://devicetree.org/schemas/display/bridge/fsl,imx8mp-hdmi-tx.yaml#
5 $schema: http://devicetree.org/meta-schemas/co 5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6 6
7 title: Freescale i.MX8MP DWC HDMI TX Encoder 7 title: Freescale i.MX8MP DWC HDMI TX Encoder
8 8
9 maintainers: 9 maintainers:
10 - Lucas Stach <l.stach@pengutronix.de> 10 - Lucas Stach <l.stach@pengutronix.de>
11 11
12 description: 12 description:
13 The i.MX8MP HDMI transmitter is a Synopsys D 13 The i.MX8MP HDMI transmitter is a Synopsys DesignWare
14 HDMI 2.0a TX controller IP. 14 HDMI 2.0a TX controller IP.
15 15
16 allOf: 16 allOf:
17 - $ref: /schemas/display/bridge/synopsys,dw- 17 - $ref: /schemas/display/bridge/synopsys,dw-hdmi.yaml#
18 18
19 properties: 19 properties:
20 compatible: 20 compatible:
21 enum: 21 enum:
22 - fsl,imx8mp-hdmi-tx 22 - fsl,imx8mp-hdmi-tx
23 23
24 reg-io-width: 24 reg-io-width:
25 const: 1 25 const: 1
26 26
27 clocks: 27 clocks:
28 maxItems: 4 28 maxItems: 4
29 29
30 clock-names: 30 clock-names:
31 items: 31 items:
32 - const: iahb 32 - const: iahb
33 - const: isfr 33 - const: isfr
34 - const: cec 34 - const: cec
35 - const: pix 35 - const: pix
36 36
37 power-domains: 37 power-domains:
38 maxItems: 1 38 maxItems: 1
39 39
40 ports: 40 ports:
41 $ref: /schemas/graph.yaml#/properties/port 41 $ref: /schemas/graph.yaml#/properties/ports
42 42
43 properties: 43 properties:
44 port@0: 44 port@0:
45 $ref: /schemas/graph.yaml#/properties/ 45 $ref: /schemas/graph.yaml#/properties/port
46 description: Parallel RGB input port 46 description: Parallel RGB input port
47 47
48 port@1: 48 port@1:
49 $ref: /schemas/graph.yaml#/properties/ 49 $ref: /schemas/graph.yaml#/properties/port
50 description: HDMI output port 50 description: HDMI output port
51 51
52 required: 52 required:
53 - port@0 53 - port@0
54 - port@1 54 - port@1
55 55
56 required: 56 required:
57 - compatible 57 - compatible
58 - reg 58 - reg
59 - clocks 59 - clocks
60 - clock-names 60 - clock-names
61 - interrupts 61 - interrupts
62 - power-domains 62 - power-domains
63 - ports 63 - ports
64 64
65 unevaluatedProperties: false 65 unevaluatedProperties: false
66 66
67 examples: 67 examples:
68 - | 68 - |
69 #include <dt-bindings/clock/imx8mp-clock.h 69 #include <dt-bindings/clock/imx8mp-clock.h>
70 #include <dt-bindings/interrupt-controller 70 #include <dt-bindings/interrupt-controller/irq.h>
71 #include <dt-bindings/power/imx8mp-power.h 71 #include <dt-bindings/power/imx8mp-power.h>
72 72
73 hdmi@32fd8000 { 73 hdmi@32fd8000 {
74 compatible = "fsl,imx8mp-hdmi-tx"; 74 compatible = "fsl,imx8mp-hdmi-tx";
75 reg = <0x32fd8000 0x7eff>; 75 reg = <0x32fd8000 0x7eff>;
76 interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; 76 interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
77 clocks = <&clk IMX8MP_CLK_HDMI_APB>, 77 clocks = <&clk IMX8MP_CLK_HDMI_APB>,
78 <&clk IMX8MP_CLK_HDMI_REF_266 78 <&clk IMX8MP_CLK_HDMI_REF_266M>,
79 <&clk IMX8MP_CLK_32K>, 79 <&clk IMX8MP_CLK_32K>,
80 <&hdmi_tx_phy>; 80 <&hdmi_tx_phy>;
81 clock-names = "iahb", "isfr", "cec", " 81 clock-names = "iahb", "isfr", "cec", "pix";
82 power-domains = <&hdmi_blk_ctrl IMX8MP 82 power-domains = <&hdmi_blk_ctrl IMX8MP_HDMIBLK_PD_HDMI_TX>;
83 reg-io-width = <1>; 83 reg-io-width = <1>;
84 ports { 84 ports {
85 #address-cells = <1>; 85 #address-cells = <1>;
86 #size-cells = <0>; 86 #size-cells = <0>;
87 port@0 { 87 port@0 {
88 reg = <0>; 88 reg = <0>;
89 89
90 hdmi_tx_from_pvi: endpoint { 90 hdmi_tx_from_pvi: endpoint {
91 remote-endpoint = <&pvi_to_hdmi 91 remote-endpoint = <&pvi_to_hdmi_tx>;
92 }; 92 };
93 }; 93 };
94 94
95 port@1 { 95 port@1 {
96 reg = <1>; 96 reg = <1>;
97 hdmi_tx_out: endpoint { 97 hdmi_tx_out: endpoint {
98 remote-endpoint = <&hdmi0_con> 98 remote-endpoint = <&hdmi0_con>;
99 }; 99 };
100 }; 100 };
101 }; 101 };
102 }; 102 };
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