1 Drivers for the second video output of the GE
2 STDP4028-ge-b850v3-fw bridges (LVDS-DP)
3 STDP2690-ge-b850v3-fw bridges (DP-DP++)
4
5 The video processing pipeline on the second ou
6
7 Host -> LVDS|--(STDP4028)--|DP -> DP|--(STD
8
9 Each bridge has a dedicated flash containing f
10 design. The result is that, in this design, ne
11 STDP2690 behave as the stock bridges would. Th
12 suffix "-ge-b850v3-fw" to make it clear that t
13 the firmware specific for the GE B850v3.
14
15 The hardware do not provide control over the v
16 two bridges behaves as a single one. The only
17 hardware are EDID, HPD, and interrupts.
18
19 stdp4028-ge-b850v3-fw required properties:
20 - compatible : "megachips,stdp4028-ge-b850v3
21 - reg : I2C bus address
22 - interrupts : one interrupt should be descr
23 <0 IRQ_TYPE_LEVEL_HIGH>
24 - ports : One input port(reg = <0>) and one
25
26 stdp2690-ge-b850v3-fw required properties:
27 compatible : "megachips,stdp2690-ge-b850v3
28 - reg : I2C bus address
29 - ports : One input port(reg = <0>) and one
30
31 Example:
32
33 &mux2_i2c2 {
34 clock-frequency = <100000>;
35
36 stdp4028@73 {
37 compatible = "megachips,stdp40
38 #address-cells = <1>;
39 #size-cells = <0>;
40
41 reg = <0x73>;
42
43 interrupt-parent = <&gpio2>;
44 interrupts = <0 IRQ_TYPE_LEVEL
45
46 ports {
47 #address-cells = <1>;
48 #size-cells = <0>;
49
50 port@0 {
51 reg = <0>;
52 stdp4028_in: e
53 remote
54 };
55 };
56 port@1 {
57 reg = <1>;
58 stdp4028_out:
59 remote
60 };
61 };
62 };
63 };
64
65 stdp2690@72 {
66 compatible = "megachips,stdp26
67 #address-cells = <1>;
68 #size-cells = <0>;
69
70 reg = <0x72>;
71
72 ports {
73 #address-cells = <1>;
74 #size-cells = <0>;
75
76 port@0 {
77 reg = <0>;
78 stdp2690_in: e
79 remote
80 };
81 };
82
83 port@1 {
84 reg = <1>;
85 stdp2690_out:
86 /* Con
87 };
88 };
89 };
90 };
91 };
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