1 Drivers for the second video output of the GE 1 Drivers for the second video output of the GE B850v3:
2 STDP4028-ge-b850v3-fw bridges (LVDS-DP) 2 STDP4028-ge-b850v3-fw bridges (LVDS-DP)
3 STDP2690-ge-b850v3-fw bridges (DP-DP++) 3 STDP2690-ge-b850v3-fw bridges (DP-DP++)
4 4
5 The video processing pipeline on the second ou 5 The video processing pipeline on the second output on the GE B850v3:
6 6
7 Host -> LVDS|--(STDP4028)--|DP -> DP|--(STD 7 Host -> LVDS|--(STDP4028)--|DP -> DP|--(STDP2690)--|DP++ -> Video output
8 8
9 Each bridge has a dedicated flash containing f 9 Each bridge has a dedicated flash containing firmware for supporting the custom
10 design. The result is that, in this design, ne 10 design. The result is that, in this design, neither the STDP4028 nor the
11 STDP2690 behave as the stock bridges would. Th 11 STDP2690 behave as the stock bridges would. The compatible strings include the
12 suffix "-ge-b850v3-fw" to make it clear that t 12 suffix "-ge-b850v3-fw" to make it clear that the driver is for the bridges with
13 the firmware specific for the GE B850v3. 13 the firmware specific for the GE B850v3.
14 14
15 The hardware do not provide control over the v 15 The hardware do not provide control over the video processing pipeline, as the
16 two bridges behaves as a single one. The only 16 two bridges behaves as a single one. The only interfaces exposed by the
17 hardware are EDID, HPD, and interrupts. 17 hardware are EDID, HPD, and interrupts.
18 18
19 stdp4028-ge-b850v3-fw required properties: 19 stdp4028-ge-b850v3-fw required properties:
20 - compatible : "megachips,stdp4028-ge-b850v3 20 - compatible : "megachips,stdp4028-ge-b850v3-fw"
21 - reg : I2C bus address 21 - reg : I2C bus address
22 - interrupts : one interrupt should be descr 22 - interrupts : one interrupt should be described here, as in
23 <0 IRQ_TYPE_LEVEL_HIGH> 23 <0 IRQ_TYPE_LEVEL_HIGH>
24 - ports : One input port(reg = <0>) and one 24 - ports : One input port(reg = <0>) and one output port(reg = <1>)
25 25
26 stdp2690-ge-b850v3-fw required properties: 26 stdp2690-ge-b850v3-fw required properties:
27 compatible : "megachips,stdp2690-ge-b850v3 27 compatible : "megachips,stdp2690-ge-b850v3-fw"
28 - reg : I2C bus address 28 - reg : I2C bus address
29 - ports : One input port(reg = <0>) and one 29 - ports : One input port(reg = <0>) and one output port(reg = <1>)
30 30
31 Example: 31 Example:
32 32
33 &mux2_i2c2 { 33 &mux2_i2c2 {
34 clock-frequency = <100000>; 34 clock-frequency = <100000>;
35 35
36 stdp4028@73 { 36 stdp4028@73 {
37 compatible = "megachips,stdp40 37 compatible = "megachips,stdp4028-ge-b850v3-fw";
38 #address-cells = <1>; 38 #address-cells = <1>;
39 #size-cells = <0>; 39 #size-cells = <0>;
40 40
41 reg = <0x73>; 41 reg = <0x73>;
42 42
43 interrupt-parent = <&gpio2>; 43 interrupt-parent = <&gpio2>;
44 interrupts = <0 IRQ_TYPE_LEVEL 44 interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
45 45
46 ports { 46 ports {
47 #address-cells = <1>; 47 #address-cells = <1>;
48 #size-cells = <0>; 48 #size-cells = <0>;
49 49
50 port@0 { 50 port@0 {
51 reg = <0>; 51 reg = <0>;
52 stdp4028_in: e 52 stdp4028_in: endpoint {
53 remote 53 remote-endpoint = <&lvds0_out>;
54 }; 54 };
55 }; 55 };
56 port@1 { 56 port@1 {
57 reg = <1>; 57 reg = <1>;
58 stdp4028_out: 58 stdp4028_out: endpoint {
59 remote 59 remote-endpoint = <&stdp2690_in>;
60 }; 60 };
61 }; 61 };
62 }; 62 };
63 }; 63 };
64 64
65 stdp2690@72 { 65 stdp2690@72 {
66 compatible = "megachips,stdp26 66 compatible = "megachips,stdp2690-ge-b850v3-fw";
67 #address-cells = <1>; 67 #address-cells = <1>;
68 #size-cells = <0>; 68 #size-cells = <0>;
69 69
70 reg = <0x72>; 70 reg = <0x72>;
71 71
72 ports { 72 ports {
73 #address-cells = <1>; 73 #address-cells = <1>;
74 #size-cells = <0>; 74 #size-cells = <0>;
75 75
76 port@0 { 76 port@0 {
77 reg = <0>; 77 reg = <0>;
78 stdp2690_in: e 78 stdp2690_in: endpoint {
79 remote 79 remote-endpoint = <&stdp4028_out>;
80 }; 80 };
81 }; 81 };
82 82
83 port@1 { 83 port@1 {
84 reg = <1>; 84 reg = <1>;
85 stdp2690_out: 85 stdp2690_out: endpoint {
86 /* Con 86 /* Connector for external display */
87 }; 87 };
88 }; 88 };
89 }; 89 };
90 }; 90 };
91 }; 91 };
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