1 # SPDX-License-Identifier: (GPL-2.0-only OR BS 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 %YAML 1.2 2 %YAML 1.2
3 --- 3 ---
4 $id: http://devicetree.org/schemas/display/bri 4 $id: http://devicetree.org/schemas/display/bridge/nwl-dsi.yaml#
5 $schema: http://devicetree.org/meta-schemas/co 5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6 6
7 title: Northwest Logic MIPI-DSI controller on 7 title: Northwest Logic MIPI-DSI controller on i.MX SoCs
8 8
9 maintainers: 9 maintainers:
10 - Guido Gúnther <agx@sigxcpu.org> 10 - Guido Gúnther <agx@sigxcpu.org>
11 - Robert Chiras <robert.chiras@nxp.com> 11 - Robert Chiras <robert.chiras@nxp.com>
12 12
13 description: | 13 description: |
14 NWL MIPI-DSI host controller found on i.MX8 14 NWL MIPI-DSI host controller found on i.MX8 platforms. This is a dsi bridge for
15 the SOCs NWL MIPI-DSI host controller. 15 the SOCs NWL MIPI-DSI host controller.
16 16
17 allOf: 17 allOf:
18 - $ref: ../dsi-controller.yaml# 18 - $ref: ../dsi-controller.yaml#
19 19
20 properties: 20 properties:
21 compatible: 21 compatible:
22 const: fsl,imx8mq-nwl-dsi 22 const: fsl,imx8mq-nwl-dsi
23 23
24 reg: 24 reg:
25 maxItems: 1 25 maxItems: 1
26 26
27 interrupts: 27 interrupts:
28 maxItems: 1 28 maxItems: 1
29 29
30 '#address-cells': 30 '#address-cells':
31 const: 1 31 const: 1
32 32
33 '#size-cells': 33 '#size-cells':
34 const: 0 34 const: 0
35 35
36 assigned-clock-parents: true 36 assigned-clock-parents: true
37 assigned-clock-rates: true 37 assigned-clock-rates: true
38 assigned-clocks: true 38 assigned-clocks: true
39 39
40 clocks: 40 clocks:
41 items: 41 items:
42 - description: DSI core clock 42 - description: DSI core clock
43 - description: RX_ESC clock (used in esc 43 - description: RX_ESC clock (used in escape mode)
44 - description: TX_ESC clock (used in esc 44 - description: TX_ESC clock (used in escape mode)
45 - description: PHY_REF clock 45 - description: PHY_REF clock
46 - description: LCDIF clock 46 - description: LCDIF clock
47 47
48 clock-names: 48 clock-names:
49 items: 49 items:
50 - const: core 50 - const: core
51 - const: rx_esc 51 - const: rx_esc
52 - const: tx_esc 52 - const: tx_esc
53 - const: phy_ref 53 - const: phy_ref
54 - const: lcdif 54 - const: lcdif
55 55
56 mux-controls: 56 mux-controls:
57 description: 57 description:
58 mux controller node to use for operating 58 mux controller node to use for operating the input mux
59 59
60 phys: 60 phys:
61 maxItems: 1 61 maxItems: 1
62 description: 62 description:
63 A phandle to the phy module representing 63 A phandle to the phy module representing the DPHY
64 64
65 phy-names: 65 phy-names:
66 items: 66 items:
67 - const: dphy 67 - const: dphy
68 68
69 power-domains: 69 power-domains:
70 maxItems: 1 70 maxItems: 1
71 71
72 resets: 72 resets:
73 items: 73 items:
74 - description: dsi byte reset line 74 - description: dsi byte reset line
75 - description: dsi dpi reset line 75 - description: dsi dpi reset line
76 - description: dsi esc reset line 76 - description: dsi esc reset line
77 - description: dsi pclk reset line 77 - description: dsi pclk reset line
78 78
79 reset-names: 79 reset-names:
80 items: 80 items:
81 - const: byte 81 - const: byte
82 - const: dpi 82 - const: dpi
83 - const: esc 83 - const: esc
84 - const: pclk 84 - const: pclk
85 85
86 ports: 86 ports:
87 $ref: /schemas/graph.yaml#/properties/port !! 87 type: object
88 !! 88 description:
>> 89 A node containing DSI input & output port nodes with endpoint
>> 90 definitions as documented in
>> 91 Documentation/devicetree/bindings/graph.txt.
89 properties: 92 properties:
90 port@0: 93 port@0:
91 $ref: /schemas/graph.yaml#/$defs/port- !! 94 type: object
92 description: 95 description:
93 Input port node to receive pixel dat 96 Input port node to receive pixel data from the
94 display controller. Exactly one endp 97 display controller. Exactly one endpoint must be
95 specified. 98 specified.
96 properties: 99 properties:
>> 100 '#address-cells':
>> 101 const: 1
>> 102
>> 103 '#size-cells':
>> 104 const: 0
>> 105
97 endpoint@0: 106 endpoint@0:
98 $ref: /schemas/graph.yaml#/propert <<
99 description: sub-node describing t 107 description: sub-node describing the input from LCDIF
>> 108 type: object
100 109
101 endpoint@1: 110 endpoint@1:
102 $ref: /schemas/graph.yaml#/propert <<
103 description: sub-node describing t 111 description: sub-node describing the input from DCSS
>> 112 type: object
>> 113
>> 114 reg:
>> 115 const: 0
>> 116
>> 117 required:
>> 118 - '#address-cells'
>> 119 - '#size-cells'
>> 120 - reg
104 121
105 oneOf: 122 oneOf:
106 - required: 123 - required:
107 - endpoint@0 124 - endpoint@0
108 - required: 125 - required:
109 - endpoint@1 126 - endpoint@1
110 127
111 unevaluatedProperties: false !! 128 additionalProperties: false
112 129
113 port@1: 130 port@1:
114 $ref: /schemas/graph.yaml#/properties/ !! 131 type: object
115 description: 132 description:
116 DSI output port node to the panel or 133 DSI output port node to the panel or the next bridge
117 in the chain 134 in the chain
118 135
>> 136 '#address-cells':
>> 137 const: 1
>> 138
>> 139 '#size-cells':
>> 140 const: 0
>> 141
119 required: 142 required:
>> 143 - '#address-cells'
>> 144 - '#size-cells'
120 - port@0 145 - port@0
121 - port@1 146 - port@1
>> 147
>> 148 additionalProperties: false
122 149
123 required: 150 required:
124 - '#address-cells' 151 - '#address-cells'
125 - '#size-cells' 152 - '#size-cells'
126 - clock-names 153 - clock-names
127 - clocks 154 - clocks
128 - compatible 155 - compatible
129 - interrupts 156 - interrupts
130 - mux-controls 157 - mux-controls
131 - phy-names 158 - phy-names
132 - phys 159 - phys
133 - ports 160 - ports
134 - reg 161 - reg
135 - reset-names 162 - reset-names
136 - resets 163 - resets
137 164
138 unevaluatedProperties: false 165 unevaluatedProperties: false
139 166
140 examples: 167 examples:
141 - | 168 - |
142 #include <dt-bindings/clock/imx8mq-clock.h 169 #include <dt-bindings/clock/imx8mq-clock.h>
143 #include <dt-bindings/gpio/gpio.h> 170 #include <dt-bindings/gpio/gpio.h>
144 #include <dt-bindings/interrupt-controller 171 #include <dt-bindings/interrupt-controller/arm-gic.h>
145 #include <dt-bindings/reset/imx8mq-reset.h 172 #include <dt-bindings/reset/imx8mq-reset.h>
146 173
147 dsi@30a00000 { 174 dsi@30a00000 {
148 #address-cells = <1>; 175 #address-cells = <1>;
149 #size-cells = <0>; 176 #size-cells = <0>;
150 compatible = "fsl,imx8mq-nwl-dsi 177 compatible = "fsl,imx8mq-nwl-dsi";
151 reg = <0x30A00000 0x300>; 178 reg = <0x30A00000 0x300>;
152 clocks = <&clk IMX8MQ_CLK_DSI_CO 179 clocks = <&clk IMX8MQ_CLK_DSI_CORE>,
153 <&clk IMX8MQ_CLK_DSI_AH 180 <&clk IMX8MQ_CLK_DSI_AHB>,
154 <&clk IMX8MQ_CLK_DSI_IP 181 <&clk IMX8MQ_CLK_DSI_IPG_DIV>,
155 <&clk IMX8MQ_CLK_DSI_PH 182 <&clk IMX8MQ_CLK_DSI_PHY_REF>,
156 <&clk IMX8MQ_CLK_LCDIF_ 183 <&clk IMX8MQ_CLK_LCDIF_PIXEL>;
157 clock-names = "core", "rx_esc", 184 clock-names = "core", "rx_esc", "tx_esc", "phy_ref", "lcdif";
158 interrupts = <GIC_SPI 34 IRQ_TYP 185 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
159 mux-controls = <&mux 0>; 186 mux-controls = <&mux 0>;
160 power-domains = <&pgc_mipi>; 187 power-domains = <&pgc_mipi>;
161 resets = <&src IMX8MQ_RESET_MIPI 188 resets = <&src IMX8MQ_RESET_MIPI_DSI_RESET_BYTE_N>,
162 <&src IMX8MQ_RESET_MIPI 189 <&src IMX8MQ_RESET_MIPI_DSI_DPI_RESET_N>,
163 <&src IMX8MQ_RESET_MIPI 190 <&src IMX8MQ_RESET_MIPI_DSI_ESC_RESET_N>,
164 <&src IMX8MQ_RESET_MIPI 191 <&src IMX8MQ_RESET_MIPI_DSI_PCLK_RESET_N>;
165 reset-names = "byte", "dpi", "es 192 reset-names = "byte", "dpi", "esc", "pclk";
166 phys = <&dphy>; 193 phys = <&dphy>;
167 phy-names = "dphy"; 194 phy-names = "dphy";
168 195
169 panel@0 { 196 panel@0 {
170 compatible = "rocktech,j 197 compatible = "rocktech,jh057n00900";
171 reg = <0>; 198 reg = <0>;
172 vcc-supply = <®_2v8_p 199 vcc-supply = <®_2v8_p>;
173 iovcc-supply = <®_1v8 200 iovcc-supply = <®_1v8_p>;
174 reset-gpios = <&gpio3 13 201 reset-gpios = <&gpio3 13 GPIO_ACTIVE_LOW>;
175 port { 202 port {
176 panel_in: endpoint 203 panel_in: endpoint {
177 remote-en 204 remote-endpoint = <&mipi_dsi_out>;
178 }; 205 };
179 }; 206 };
180 }; 207 };
181 208
182 ports { 209 ports {
183 #address-cells = <1>; 210 #address-cells = <1>;
184 #size-cells = <0>; 211 #size-cells = <0>;
185 212
186 port@0 { 213 port@0 {
187 #size-cells = <0>; 214 #size-cells = <0>;
188 #address-cells = <1 215 #address-cells = <1>;
189 reg = <0>; 216 reg = <0>;
190 mipi_dsi_in: endpoi 217 mipi_dsi_in: endpoint@0 {
191 reg = 218 reg = <0>;
192 remote 219 remote-endpoint = <&lcdif_mipi_dsi>;
193 }; 220 };
194 }; 221 };
195 port@1 { 222 port@1 {
196 reg = <1>; 223 reg = <1>;
197 mipi_dsi_out: endpo 224 mipi_dsi_out: endpoint {
198 remot 225 remote-endpoint = <&panel_in>;
199 }; 226 };
200 }; 227 };
201 }; 228 };
202 }; 229 };
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