1 # SPDX-License-Identifier: (GPL-2.0-only OR BS 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 %YAML 1.2 2 %YAML 1.2
3 --- 3 ---
4 $id: http://devicetree.org/schemas/display/bri 4 $id: http://devicetree.org/schemas/display/bridge/nwl-dsi.yaml#
5 $schema: http://devicetree.org/meta-schemas/co 5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6 6
7 title: Northwest Logic MIPI-DSI controller on 7 title: Northwest Logic MIPI-DSI controller on i.MX SoCs
8 8
9 maintainers: 9 maintainers:
10 - Guido Gúnther <agx@sigxcpu.org> 10 - Guido Gúnther <agx@sigxcpu.org>
11 - Robert Chiras <robert.chiras@nxp.com> 11 - Robert Chiras <robert.chiras@nxp.com>
12 12
13 description: | 13 description: |
14 NWL MIPI-DSI host controller found on i.MX8 14 NWL MIPI-DSI host controller found on i.MX8 platforms. This is a dsi bridge for
15 the SOCs NWL MIPI-DSI host controller. 15 the SOCs NWL MIPI-DSI host controller.
16 16
17 allOf: <<
18 - $ref: ../dsi-controller.yaml# <<
19 <<
20 properties: 17 properties:
21 compatible: 18 compatible:
22 const: fsl,imx8mq-nwl-dsi 19 const: fsl,imx8mq-nwl-dsi
23 20
24 reg: 21 reg:
25 maxItems: 1 22 maxItems: 1
26 23
27 interrupts: 24 interrupts:
28 maxItems: 1 25 maxItems: 1
29 26
30 '#address-cells': 27 '#address-cells':
31 const: 1 28 const: 1
32 29
33 '#size-cells': 30 '#size-cells':
34 const: 0 31 const: 0
35 32
36 assigned-clock-parents: true <<
37 assigned-clock-rates: true <<
38 assigned-clocks: true <<
39 <<
40 clocks: 33 clocks:
41 items: 34 items:
42 - description: DSI core clock 35 - description: DSI core clock
43 - description: RX_ESC clock (used in esc 36 - description: RX_ESC clock (used in escape mode)
44 - description: TX_ESC clock (used in esc 37 - description: TX_ESC clock (used in escape mode)
45 - description: PHY_REF clock 38 - description: PHY_REF clock
46 - description: LCDIF clock 39 - description: LCDIF clock
47 40
48 clock-names: 41 clock-names:
49 items: 42 items:
50 - const: core 43 - const: core
51 - const: rx_esc 44 - const: rx_esc
52 - const: tx_esc 45 - const: tx_esc
53 - const: phy_ref 46 - const: phy_ref
54 - const: lcdif 47 - const: lcdif
55 48
56 mux-controls: 49 mux-controls:
57 description: 50 description:
58 mux controller node to use for operating 51 mux controller node to use for operating the input mux
59 52
60 phys: 53 phys:
61 maxItems: 1 54 maxItems: 1
62 description: 55 description:
63 A phandle to the phy module representing 56 A phandle to the phy module representing the DPHY
64 57
65 phy-names: 58 phy-names:
66 items: 59 items:
67 - const: dphy 60 - const: dphy
68 61
69 power-domains: 62 power-domains:
70 maxItems: 1 63 maxItems: 1
71 64
72 resets: 65 resets:
73 items: 66 items:
74 - description: dsi byte reset line 67 - description: dsi byte reset line
75 - description: dsi dpi reset line 68 - description: dsi dpi reset line
76 - description: dsi esc reset line 69 - description: dsi esc reset line
77 - description: dsi pclk reset line 70 - description: dsi pclk reset line
78 71
79 reset-names: 72 reset-names:
80 items: 73 items:
81 - const: byte 74 - const: byte
82 - const: dpi 75 - const: dpi
83 - const: esc 76 - const: esc
84 - const: pclk 77 - const: pclk
85 78
86 ports: 79 ports:
87 $ref: /schemas/graph.yaml#/properties/port !! 80 type: object
88 !! 81 description:
>> 82 A node containing DSI input & output port nodes with endpoint
>> 83 definitions as documented in
>> 84 Documentation/devicetree/bindings/graph.txt.
89 properties: 85 properties:
90 port@0: 86 port@0:
91 $ref: /schemas/graph.yaml#/$defs/port- !! 87 type: object
92 description: 88 description:
93 Input port node to receive pixel dat 89 Input port node to receive pixel data from the
94 display controller. Exactly one endp 90 display controller. Exactly one endpoint must be
95 specified. 91 specified.
96 properties: 92 properties:
>> 93 '#address-cells':
>> 94 const: 1
>> 95
>> 96 '#size-cells':
>> 97 const: 0
>> 98
97 endpoint@0: 99 endpoint@0:
98 $ref: /schemas/graph.yaml#/propert <<
99 description: sub-node describing t 100 description: sub-node describing the input from LCDIF
>> 101 type: object
100 102
101 endpoint@1: 103 endpoint@1:
102 $ref: /schemas/graph.yaml#/propert <<
103 description: sub-node describing t 104 description: sub-node describing the input from DCSS
>> 105 type: object
>> 106
>> 107 reg:
>> 108 const: 0
>> 109
>> 110 required:
>> 111 - '#address-cells'
>> 112 - '#size-cells'
>> 113 - reg
104 114
105 oneOf: 115 oneOf:
106 - required: 116 - required:
107 - endpoint@0 117 - endpoint@0
108 - required: 118 - required:
109 - endpoint@1 119 - endpoint@1
110 120
111 unevaluatedProperties: false !! 121 additionalProperties: false
112 122
113 port@1: 123 port@1:
114 $ref: /schemas/graph.yaml#/properties/ !! 124 type: object
115 description: 125 description:
116 DSI output port node to the panel or 126 DSI output port node to the panel or the next bridge
117 in the chain 127 in the chain
118 128
>> 129 '#address-cells':
>> 130 const: 1
>> 131
>> 132 '#size-cells':
>> 133 const: 0
>> 134
119 required: 135 required:
>> 136 - '#address-cells'
>> 137 - '#size-cells'
120 - port@0 138 - port@0
121 - port@1 139 - port@1
122 140
>> 141 additionalProperties: false
>> 142
>> 143 patternProperties:
>> 144 "^panel@[0-9]+$":
>> 145 type: object
>> 146
123 required: 147 required:
124 - '#address-cells' 148 - '#address-cells'
125 - '#size-cells' 149 - '#size-cells'
126 - clock-names 150 - clock-names
127 - clocks 151 - clocks
128 - compatible 152 - compatible
129 - interrupts 153 - interrupts
130 - mux-controls 154 - mux-controls
131 - phy-names 155 - phy-names
132 - phys 156 - phys
133 - ports 157 - ports
134 - reg 158 - reg
135 - reset-names 159 - reset-names
136 - resets 160 - resets
137 161
138 unevaluatedProperties: false !! 162 additionalProperties: false
139 163
140 examples: 164 examples:
141 - | !! 165 - |
142 #include <dt-bindings/clock/imx8mq-clock.h !! 166
143 #include <dt-bindings/gpio/gpio.h> !! 167 #include <dt-bindings/clock/imx8mq-clock.h>
144 #include <dt-bindings/interrupt-controller !! 168 #include <dt-bindings/interrupt-controller/arm-gic.h>
145 #include <dt-bindings/reset/imx8mq-reset.h !! 169 #include <dt-bindings/reset/imx8mq-reset.h>
146 170
147 dsi@30a00000 { !! 171 mipi_dsi: mipi_dsi@30a00000 {
148 #address-cells = <1>; 172 #address-cells = <1>;
149 #size-cells = <0>; 173 #size-cells = <0>;
150 compatible = "fsl,imx8mq-nwl-dsi 174 compatible = "fsl,imx8mq-nwl-dsi";
151 reg = <0x30A00000 0x300>; 175 reg = <0x30A00000 0x300>;
152 clocks = <&clk IMX8MQ_CLK_DSI_CO 176 clocks = <&clk IMX8MQ_CLK_DSI_CORE>,
153 <&clk IMX8MQ_CLK_DSI_AH 177 <&clk IMX8MQ_CLK_DSI_AHB>,
154 <&clk IMX8MQ_CLK_DSI_IP 178 <&clk IMX8MQ_CLK_DSI_IPG_DIV>,
155 <&clk IMX8MQ_CLK_DSI_PH 179 <&clk IMX8MQ_CLK_DSI_PHY_REF>,
156 <&clk IMX8MQ_CLK_LCDIF_ 180 <&clk IMX8MQ_CLK_LCDIF_PIXEL>;
157 clock-names = "core", "rx_esc", 181 clock-names = "core", "rx_esc", "tx_esc", "phy_ref", "lcdif";
158 interrupts = <GIC_SPI 34 IRQ_TYP 182 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
159 mux-controls = <&mux 0>; 183 mux-controls = <&mux 0>;
160 power-domains = <&pgc_mipi>; 184 power-domains = <&pgc_mipi>;
161 resets = <&src IMX8MQ_RESET_MIPI 185 resets = <&src IMX8MQ_RESET_MIPI_DSI_RESET_BYTE_N>,
162 <&src IMX8MQ_RESET_MIPI 186 <&src IMX8MQ_RESET_MIPI_DSI_DPI_RESET_N>,
163 <&src IMX8MQ_RESET_MIPI 187 <&src IMX8MQ_RESET_MIPI_DSI_ESC_RESET_N>,
164 <&src IMX8MQ_RESET_MIPI 188 <&src IMX8MQ_RESET_MIPI_DSI_PCLK_RESET_N>;
165 reset-names = "byte", "dpi", "es 189 reset-names = "byte", "dpi", "esc", "pclk";
166 phys = <&dphy>; 190 phys = <&dphy>;
167 phy-names = "dphy"; 191 phy-names = "dphy";
168 192
169 panel@0 { 193 panel@0 {
>> 194 #address-cells = <1>;
>> 195 #size-cells = <0>;
170 compatible = "rocktech,j 196 compatible = "rocktech,jh057n00900";
171 reg = <0>; 197 reg = <0>;
172 vcc-supply = <®_2v8_p !! 198 port@0 {
173 iovcc-supply = <®_1v8 !! 199 reg = <0>;
174 reset-gpios = <&gpio3 13 <<
175 port { <<
176 panel_in: endpoint 200 panel_in: endpoint {
177 remote-en 201 remote-endpoint = <&mipi_dsi_out>;
178 }; 202 };
179 }; 203 };
180 }; 204 };
181 205
182 ports { 206 ports {
183 #address-cells = <1>; 207 #address-cells = <1>;
184 #size-cells = <0>; 208 #size-cells = <0>;
185 209
186 port@0 { 210 port@0 {
187 #size-cells = <0>; 211 #size-cells = <0>;
188 #address-cells = <1 212 #address-cells = <1>;
189 reg = <0>; 213 reg = <0>;
190 mipi_dsi_in: endpoi 214 mipi_dsi_in: endpoint@0 {
191 reg = 215 reg = <0>;
192 remote 216 remote-endpoint = <&lcdif_mipi_dsi>;
193 }; 217 };
194 }; 218 };
195 port@1 { 219 port@1 {
196 reg = <1>; 220 reg = <1>;
197 mipi_dsi_out: endpo 221 mipi_dsi_out: endpoint {
198 remot 222 remote-endpoint = <&panel_in>;
199 }; 223 };
200 }; 224 };
201 }; 225 };
202 }; !! 226 };
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