1 # SPDX-License-Identifier: (GPL-2.0-only OR BS 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 %YAML 1.2 2 %YAML 1.2
3 --- 3 ---
4 $id: http://devicetree.org/schemas/display/bri 4 $id: http://devicetree.org/schemas/display/bridge/synopsys,dw-hdmi.yaml#
5 $schema: http://devicetree.org/meta-schemas/co 5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6 6
7 title: Common Properties for Synopsys DesignWa 7 title: Common Properties for Synopsys DesignWare HDMI TX Controller
8 8
9 maintainers: 9 maintainers:
10 - Laurent Pinchart <laurent.pinchart+renesas@ 10 - Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
11 11
12 description: | 12 description: |
13 This document defines device tree properties 13 This document defines device tree properties for the Synopsys DesignWare HDMI
14 TX controller (DWC HDMI TX) IP core. It does 14 TX controller (DWC HDMI TX) IP core. It doesn't constitute a full device tree
15 binding specification by itself but is meant 15 binding specification by itself but is meant to be referenced by device tree
16 bindings for the platform-specific integrati 16 bindings for the platform-specific integrations of the DWC HDMI TX.
17 17
18 When referenced from platform device tree bi 18 When referenced from platform device tree bindings the properties defined in
19 this document are defined as follows. The pl 19 this document are defined as follows. The platform device tree bindings are
20 responsible for defining whether each proper 20 responsible for defining whether each property is required or optional.
21 21
22 properties: 22 properties:
23 reg: 23 reg:
24 maxItems: 1 24 maxItems: 1
25 25
26 reg-io-width: 26 reg-io-width:
27 description: 27 description:
28 Width (in bytes) of the registers specif 28 Width (in bytes) of the registers specified by the reg property.
29 enum: [1, 4] 29 enum: [1, 4]
30 default: 1 30 default: 1
31 31
32 clocks: 32 clocks:
33 minItems: 2 33 minItems: 2
34 maxItems: 5 34 maxItems: 5
35 items: 35 items:
36 - description: The bus clock for either 36 - description: The bus clock for either AHB and APB
37 - description: The internal register con 37 - description: The internal register configuration clock
38 additionalItems: true 38 additionalItems: true
39 39
40 clock-names: 40 clock-names:
41 minItems: 2 41 minItems: 2
42 maxItems: 5 42 maxItems: 5
43 items: 43 items:
44 - const: iahb 44 - const: iahb
45 - const: isfr 45 - const: isfr
46 additionalItems: true 46 additionalItems: true
47 47
48 ddc-i2c-bus: 48 ddc-i2c-bus:
49 $ref: /schemas/types.yaml#/definitions/pha 49 $ref: /schemas/types.yaml#/definitions/phandle
50 deprecated: true 50 deprecated: true
51 description: 51 description:
52 The HDMI DDC bus can be connected to eit 52 The HDMI DDC bus can be connected to either a system I2C master or the
53 functionally-reduced I2C master containe 53 functionally-reduced I2C master contained in the DWC HDMI. When connected
54 to a system I2C master this property con 54 to a system I2C master this property contains a phandle to that I2C
55 master controller. 55 master controller.
56 56
57 This property is deprecated, the system 57 This property is deprecated, the system I2C master controller should
58 be referenced through the ddc-i2c-bus pr 58 be referenced through the ddc-i2c-bus property of the HDMI connector
59 node. 59 node.
60 60
61 interrupts: 61 interrupts:
62 maxItems: 1 62 maxItems: 1
63 63
64 additionalProperties: true 64 additionalProperties: true
65 65
66 ... 66 ...
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