1 # SPDX-License-Identifier: (GPL-2.0-only OR BS 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 %YAML 1.2 2 %YAML 1.2
3 --- 3 ---
4 $id: http://devicetree.org/schemas/display/med 4 $id: http://devicetree.org/schemas/display/mediatek/mediatek,dpi.yaml#
5 $schema: http://devicetree.org/meta-schemas/co 5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6 6
7 title: MediaTek DPI and DP_INTF Controller 7 title: MediaTek DPI and DP_INTF Controller
8 8
9 maintainers: 9 maintainers:
10 - CK Hu <ck.hu@mediatek.com> 10 - CK Hu <ck.hu@mediatek.com>
11 - Jitao shi <jitao.shi@mediatek.com> 11 - Jitao shi <jitao.shi@mediatek.com>
12 12
13 description: | 13 description: |
14 The MediaTek DPI and DP_INTF function blocks 14 The MediaTek DPI and DP_INTF function blocks are a sink of the display
15 subsystem and provides 8-bit RGB/YUV444 or 8 15 subsystem and provides 8-bit RGB/YUV444 or 8/10/10-bit YUV422 pixel data on a
16 parallel output bus. 16 parallel output bus.
17 17
18 properties: 18 properties:
19 compatible: 19 compatible:
20 oneOf: 20 oneOf:
21 - enum: 21 - enum:
22 - mediatek,mt2701-dpi 22 - mediatek,mt2701-dpi
23 - mediatek,mt7623-dpi 23 - mediatek,mt7623-dpi
24 - mediatek,mt8173-dpi 24 - mediatek,mt8173-dpi
25 - mediatek,mt8183-dpi 25 - mediatek,mt8183-dpi
26 - mediatek,mt8186-dpi 26 - mediatek,mt8186-dpi
27 - mediatek,mt8188-dp-intf 27 - mediatek,mt8188-dp-intf
28 - mediatek,mt8192-dpi 28 - mediatek,mt8192-dpi
29 - mediatek,mt8195-dp-intf 29 - mediatek,mt8195-dp-intf
30 - items: 30 - items:
31 - enum: 31 - enum:
32 - mediatek,mt6795-dpi 32 - mediatek,mt6795-dpi
33 - const: mediatek,mt8183-dpi 33 - const: mediatek,mt8183-dpi
34 - items: 34 - items:
35 - enum: 35 - enum:
36 - mediatek,mt8365-dpi 36 - mediatek,mt8365-dpi
37 - const: mediatek,mt8192-dpi 37 - const: mediatek,mt8192-dpi
38 38
39 reg: 39 reg:
40 maxItems: 1 40 maxItems: 1
41 41
42 interrupts: 42 interrupts:
43 maxItems: 1 43 maxItems: 1
44 44
45 clocks: 45 clocks:
46 items: 46 items:
47 - description: Pixel Clock 47 - description: Pixel Clock
48 - description: Engine Clock 48 - description: Engine Clock
49 - description: DPI PLL 49 - description: DPI PLL
50 50
51 clock-names: 51 clock-names:
52 items: 52 items:
53 - const: pixel 53 - const: pixel
54 - const: engine 54 - const: engine
55 - const: pll 55 - const: pll
56 56
57 pinctrl-0: true 57 pinctrl-0: true
58 pinctrl-1: true 58 pinctrl-1: true
59 59
60 pinctrl-names: 60 pinctrl-names:
61 items: 61 items:
62 - const: default 62 - const: default
63 - const: sleep 63 - const: sleep
64 64
65 power-domains: 65 power-domains:
66 description: | 66 description: |
67 The MediaTek DPI module is typically ass 67 The MediaTek DPI module is typically associated with one of the
68 following multimedia power domains: 68 following multimedia power domains:
69 POWER_DOMAIN_DISPLAY 69 POWER_DOMAIN_DISPLAY
70 POWER_DOMAIN_VDOSYS 70 POWER_DOMAIN_VDOSYS
71 POWER_DOMAIN_MM 71 POWER_DOMAIN_MM
72 The specific power domain used varies de 72 The specific power domain used varies depending on the SoC design.
73 73
74 It is recommended to explicitly add the 74 It is recommended to explicitly add the appropriate power domain
75 property to the DPI node in the device t 75 property to the DPI node in the device tree.
76 maxItems: 1 76 maxItems: 1
77 77
78 port: 78 port:
79 $ref: /schemas/graph.yaml#/properties/port 79 $ref: /schemas/graph.yaml#/properties/port
80 description: 80 description:
81 Output port node. This port should be co 81 Output port node. This port should be connected to the input port of an
82 attached HDMI, LVDS or DisplayPort encod 82 attached HDMI, LVDS or DisplayPort encoder chip.
83 83
84 required: 84 required:
85 - compatible 85 - compatible
86 - reg 86 - reg
87 - interrupts 87 - interrupts
88 - clocks 88 - clocks
89 - clock-names 89 - clock-names
90 - port 90 - port
91 91
92 additionalProperties: false 92 additionalProperties: false
93 93
94 examples: 94 examples:
95 - | 95 - |
96 #include <dt-bindings/interrupt-controller 96 #include <dt-bindings/interrupt-controller/arm-gic.h>
97 #include <dt-bindings/clock/mt8173-clk.h> 97 #include <dt-bindings/clock/mt8173-clk.h>
98 98
99 dpi0: dpi@1401d000 { 99 dpi0: dpi@1401d000 {
100 compatible = "mediatek,mt8173-dpi"; 100 compatible = "mediatek,mt8173-dpi";
101 reg = <0x1401d000 0x1000>; 101 reg = <0x1401d000 0x1000>;
102 interrupts = <GIC_SPI 194 IRQ_TYPE_LEV 102 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>;
103 clocks = <&mmsys CLK_MM_DPI_PIXEL>, 103 clocks = <&mmsys CLK_MM_DPI_PIXEL>,
104 <&mmsys CLK_MM_DPI_ENGINE>, 104 <&mmsys CLK_MM_DPI_ENGINE>,
105 <&apmixedsys CLK_APMIXED_TVDPLL>; 105 <&apmixedsys CLK_APMIXED_TVDPLL>;
106 clock-names = "pixel", "engine", "pll" 106 clock-names = "pixel", "engine", "pll";
107 pinctrl-names = "default", "sleep"; 107 pinctrl-names = "default", "sleep";
108 pinctrl-0 = <&dpi_pin_func>; 108 pinctrl-0 = <&dpi_pin_func>;
109 pinctrl-1 = <&dpi_pin_idle>; 109 pinctrl-1 = <&dpi_pin_idle>;
110 110
111 port { 111 port {
112 dpi0_out: endpoint { 112 dpi0_out: endpoint {
113 remote-endpoint = <&hdmi0_in>; 113 remote-endpoint = <&hdmi0_in>;
114 }; 114 };
115 }; 115 };
116 }; 116 };
117 117
118 ... 118 ...
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