1 # SPDX-License-Identifier: (GPL-2.0-only OR BS 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 %YAML 1.2 2 %YAML 1.2
3 --- 3 ---
4 $id: http://devicetree.org/schemas/display/med 4 $id: http://devicetree.org/schemas/display/mediatek/mediatek,ethdr.yaml#
5 $schema: http://devicetree.org/meta-schemas/co 5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6 6
7 title: MediaTek Ethdr Device 7 title: MediaTek Ethdr Device
8 8
9 maintainers: 9 maintainers:
10 - Chun-Kuang Hu <chunkuang.hu@kernel.org> 10 - Chun-Kuang Hu <chunkuang.hu@kernel.org>
11 - Philipp Zabel <p.zabel@pengutronix.de> 11 - Philipp Zabel <p.zabel@pengutronix.de>
12 12
13 description: 13 description:
14 ETHDR (ET High Dynamic Range) is a MediaTek 14 ETHDR (ET High Dynamic Range) is a MediaTek internal HDR engine and is
15 designed for HDR video and graphics conversi 15 designed for HDR video and graphics conversion in the external display path.
16 It handles multiple HDR input types and perf 16 It handles multiple HDR input types and performs tone mapping, color
17 space/color format conversion, and then comb 17 space/color format conversion, and then combine different layers,
18 output the required HDR or SDR signal to the 18 output the required HDR or SDR signal to the subsequent display path.
19 This engine is composed of two video fronten 19 This engine is composed of two video frontends, two graphic frontends,
20 one video backend and a mixer. ETHDR has two 20 one video backend and a mixer. ETHDR has two DMA function blocks, DS and ADL.
21 These two function blocks read the pre-progr 21 These two function blocks read the pre-programmed registers from DRAM and
22 set them to HW in the v-blanking period. 22 set them to HW in the v-blanking period.
23 23
24 properties: 24 properties:
25 compatible: 25 compatible:
26 oneOf: 26 oneOf:
27 - const: mediatek,mt8195-disp-ethdr 27 - const: mediatek,mt8195-disp-ethdr
28 - items: 28 - items:
29 - const: mediatek,mt8188-disp-ethdr 29 - const: mediatek,mt8188-disp-ethdr
30 - const: mediatek,mt8195-disp-ethdr 30 - const: mediatek,mt8195-disp-ethdr
31 31
32 reg: 32 reg:
33 maxItems: 7 33 maxItems: 7
34 34
35 reg-names: 35 reg-names:
36 items: 36 items:
37 - const: mixer 37 - const: mixer
38 - const: vdo_fe0 38 - const: vdo_fe0
39 - const: vdo_fe1 39 - const: vdo_fe1
40 - const: gfx_fe0 40 - const: gfx_fe0
41 - const: gfx_fe1 41 - const: gfx_fe1
42 - const: vdo_be 42 - const: vdo_be
43 - const: adl_ds 43 - const: adl_ds
44 44
45 interrupts: 45 interrupts:
46 maxItems: 1 46 maxItems: 1
47 47
48 iommus: 48 iommus:
49 minItems: 1 49 minItems: 1
50 maxItems: 2 50 maxItems: 2
51 51
52 clocks: 52 clocks:
53 items: 53 items:
54 - description: mixer clock 54 - description: mixer clock
55 - description: video frontend 0 clock 55 - description: video frontend 0 clock
56 - description: video frontend 1 clock 56 - description: video frontend 1 clock
57 - description: graphic frontend 0 clock 57 - description: graphic frontend 0 clock
58 - description: graphic frontend 1 clock 58 - description: graphic frontend 1 clock
59 - description: video backend clock 59 - description: video backend clock
60 - description: autodownload and menuload 60 - description: autodownload and menuload clock
61 - description: video frontend 0 async cl 61 - description: video frontend 0 async clock
62 - description: video frontend 1 async cl 62 - description: video frontend 1 async clock
63 - description: graphic frontend 0 async 63 - description: graphic frontend 0 async clock
64 - description: graphic frontend 1 async 64 - description: graphic frontend 1 async clock
65 - description: video backend async clock 65 - description: video backend async clock
66 - description: ethdr top clock 66 - description: ethdr top clock
67 67
68 clock-names: 68 clock-names:
69 items: 69 items:
70 - const: mixer 70 - const: mixer
71 - const: vdo_fe0 71 - const: vdo_fe0
72 - const: vdo_fe1 72 - const: vdo_fe1
73 - const: gfx_fe0 73 - const: gfx_fe0
74 - const: gfx_fe1 74 - const: gfx_fe1
75 - const: vdo_be 75 - const: vdo_be
76 - const: adl_ds 76 - const: adl_ds
77 - const: vdo_fe0_async 77 - const: vdo_fe0_async
78 - const: vdo_fe1_async 78 - const: vdo_fe1_async
79 - const: gfx_fe0_async 79 - const: gfx_fe0_async
80 - const: gfx_fe1_async 80 - const: gfx_fe1_async
81 - const: vdo_be_async 81 - const: vdo_be_async
82 - const: ethdr_top 82 - const: ethdr_top
83 83
84 power-domains: 84 power-domains:
85 maxItems: 1 85 maxItems: 1
86 86
87 resets: 87 resets:
88 items: 88 items:
89 - description: video frontend 0 async re 89 - description: video frontend 0 async reset
90 - description: video frontend 1 async re 90 - description: video frontend 1 async reset
91 - description: graphic frontend 0 async 91 - description: graphic frontend 0 async reset
92 - description: graphic frontend 1 async 92 - description: graphic frontend 1 async reset
93 - description: video backend async reset 93 - description: video backend async reset
94 94
95 reset-names: 95 reset-names:
96 items: 96 items:
97 - const: vdo_fe0_async 97 - const: vdo_fe0_async
98 - const: vdo_fe1_async 98 - const: vdo_fe1_async
99 - const: gfx_fe0_async 99 - const: gfx_fe0_async
100 - const: gfx_fe1_async 100 - const: gfx_fe1_async
101 - const: vdo_be_async 101 - const: vdo_be_async
102 102
103 mediatek,gce-client-reg: 103 mediatek,gce-client-reg:
104 $ref: /schemas/types.yaml#/definitions/pha 104 $ref: /schemas/types.yaml#/definitions/phandle-array
105 minItems: 1 105 minItems: 1
106 maxItems: 7 106 maxItems: 7
107 description: The register of display funct 107 description: The register of display function block to be set by gce.
108 There are 4 arguments in this property, 108 There are 4 arguments in this property, gce node, subsys id, offset and
109 register size. The subsys id is defined 109 register size. The subsys id is defined in the gce header of each chips
110 include/dt-bindings/gce/<chip>-gce.h, ma 110 include/dt-bindings/gce/<chip>-gce.h, mapping to the register of display
111 function block. 111 function block.
112 112
113 required: 113 required:
114 - compatible 114 - compatible
115 - reg 115 - reg
116 - clocks 116 - clocks
117 - clock-names 117 - clock-names
118 - interrupts 118 - interrupts
119 - power-domains 119 - power-domains
120 - resets 120 - resets
121 - mediatek,gce-client-reg 121 - mediatek,gce-client-reg
122 122
123 additionalProperties: false 123 additionalProperties: false
124 124
125 examples: 125 examples:
126 - | 126 - |
127 #include <dt-bindings/interrupt-controller 127 #include <dt-bindings/interrupt-controller/arm-gic.h>
128 #include <dt-bindings/clock/mt8195-clk.h> 128 #include <dt-bindings/clock/mt8195-clk.h>
129 #include <dt-bindings/gce/mt8195-gce.h> 129 #include <dt-bindings/gce/mt8195-gce.h>
130 #include <dt-bindings/memory/mt8195-memory 130 #include <dt-bindings/memory/mt8195-memory-port.h>
131 #include <dt-bindings/power/mt8195-power.h 131 #include <dt-bindings/power/mt8195-power.h>
132 #include <dt-bindings/reset/mt8195-resets. 132 #include <dt-bindings/reset/mt8195-resets.h>
133 133
134 soc { 134 soc {
135 #address-cells = <2>; 135 #address-cells = <2>;
136 #size-cells = <2>; 136 #size-cells = <2>;
137 137
138 hdr-engine@1c114000 { 138 hdr-engine@1c114000 {
139 compatible = "mediatek,mt8195- 139 compatible = "mediatek,mt8195-disp-ethdr";
140 reg = <0 0x1c114000 0 0x1000>, 140 reg = <0 0x1c114000 0 0x1000>,
141 <0 0x1c115000 0 0x1000>, 141 <0 0x1c115000 0 0x1000>,
142 <0 0x1c117000 0 0x1000>, 142 <0 0x1c117000 0 0x1000>,
143 <0 0x1c119000 0 0x1000>, 143 <0 0x1c119000 0 0x1000>,
144 <0 0x1c11a000 0 0x1000>, 144 <0 0x1c11a000 0 0x1000>,
145 <0 0x1c11b000 0 0x1000>, 145 <0 0x1c11b000 0 0x1000>,
146 <0 0x1c11c000 0 0x1000>; 146 <0 0x1c11c000 0 0x1000>;
147 reg-names = "mixer", "vdo_fe0" 147 reg-names = "mixer", "vdo_fe0", "vdo_fe1", "gfx_fe0", "gfx_fe1",
148 "vdo_be", "adl_ds" 148 "vdo_be", "adl_ds";
149 mediatek,gce-client-reg = <&gc 149 mediatek,gce-client-reg = <&gce0 SUBSYS_1c11XXXX 0x4000 0x1000>,
150 <&gc 150 <&gce0 SUBSYS_1c11XXXX 0x5000 0x1000>,
151 <&gc 151 <&gce0 SUBSYS_1c11XXXX 0x7000 0x1000>,
152 <&gc 152 <&gce0 SUBSYS_1c11XXXX 0x9000 0x1000>,
153 <&gc 153 <&gce0 SUBSYS_1c11XXXX 0xa000 0x1000>,
154 <&gc 154 <&gce0 SUBSYS_1c11XXXX 0xb000 0x1000>,
155 <&gc 155 <&gce0 SUBSYS_1c11XXXX 0xc000 0x1000>;
156 clocks = <&vdosys1 CLK_VDO1_DI 156 clocks = <&vdosys1 CLK_VDO1_DISP_MIXER>,
157 <&vdosys1 CLK_VDO1_HD 157 <&vdosys1 CLK_VDO1_HDR_VDO_FE0>,
158 <&vdosys1 CLK_VDO1_HD 158 <&vdosys1 CLK_VDO1_HDR_VDO_FE1>,
159 <&vdosys1 CLK_VDO1_HD 159 <&vdosys1 CLK_VDO1_HDR_GFX_FE0>,
160 <&vdosys1 CLK_VDO1_HD 160 <&vdosys1 CLK_VDO1_HDR_GFX_FE1>,
161 <&vdosys1 CLK_VDO1_HD 161 <&vdosys1 CLK_VDO1_HDR_VDO_BE>,
162 <&vdosys1 CLK_VDO1_26 162 <&vdosys1 CLK_VDO1_26M_SLOW>,
163 <&vdosys1 CLK_VDO1_HD 163 <&vdosys1 CLK_VDO1_HDR_VDO_FE0_DL_ASYNC>,
164 <&vdosys1 CLK_VDO1_HD 164 <&vdosys1 CLK_VDO1_HDR_VDO_FE1_DL_ASYNC>,
165 <&vdosys1 CLK_VDO1_HD 165 <&vdosys1 CLK_VDO1_HDR_GFX_FE0_DL_ASYNC>,
166 <&vdosys1 CLK_VDO1_HD 166 <&vdosys1 CLK_VDO1_HDR_GFX_FE1_DL_ASYNC>,
167 <&vdosys1 CLK_VDO1_HD 167 <&vdosys1 CLK_VDO1_HDR_VDO_BE_DL_ASYNC>,
168 <&topckgen CLK_TOP_ET 168 <&topckgen CLK_TOP_ETHDR>;
169 clock-names = "mixer", "vdo_fe 169 clock-names = "mixer", "vdo_fe0", "vdo_fe1", "gfx_fe0", "gfx_fe1",
170 "vdo_be", "adl_d 170 "vdo_be", "adl_ds", "vdo_fe0_async", "vdo_fe1_async",
171 "gfx_fe0_async", 171 "gfx_fe0_async", "gfx_fe1_async","vdo_be_async",
172 "ethdr_top"; 172 "ethdr_top";
173 power-domains = <&spm MT8195_P 173 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
174 iommus = <&iommu_vpp M4U_PORT_ 174 iommus = <&iommu_vpp M4U_PORT_L3_HDR_DS>,
175 <&iommu_vpp M4U_PORT_ 175 <&iommu_vpp M4U_PORT_L3_HDR_ADL>;
176 interrupts = <GIC_SPI 517 IRQ_ 176 interrupts = <GIC_SPI 517 IRQ_TYPE_LEVEL_HIGH 0>; /* disp mixer */
177 resets = <&vdosys1 MT8195_VDOS 177 resets = <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE0_DL_ASYNC>,
178 <&vdosys1 MT8195_VDOS 178 <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE1_DL_ASYNC>,
179 <&vdosys1 MT8195_VDOS 179 <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE0_DL_ASYNC>,
180 <&vdosys1 MT8195_VDOS 180 <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE1_DL_ASYNC>,
181 <&vdosys1 MT8195_VDOS 181 <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_BE_DL_ASYNC>;
182 reset-names = "vdo_fe0_async", 182 reset-names = "vdo_fe0_async", "vdo_fe1_async", "gfx_fe0_async",
183 "gfx_fe1_async", 183 "gfx_fe1_async", "vdo_be_async";
184 }; 184 };
185 }; 185 };
186 ... 186 ...
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