1 # SPDX-License-Identifier: (GPL-2.0-only OR BS 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 %YAML 1.2 2 %YAML 1.2
3 --- 3 ---
4 $id: http://devicetree.org/schemas/display/med 4 $id: http://devicetree.org/schemas/display/mediatek/mediatek,merge.yaml#
5 $schema: http://devicetree.org/meta-schemas/co 5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6 6
7 title: Mediatek display merge 7 title: Mediatek display merge
8 8
9 maintainers: 9 maintainers:
10 - Chun-Kuang Hu <chunkuang.hu@kernel.org> 10 - Chun-Kuang Hu <chunkuang.hu@kernel.org>
11 - Philipp Zabel <p.zabel@pengutronix.de> 11 - Philipp Zabel <p.zabel@pengutronix.de>
12 12
13 description: | 13 description: |
14 Mediatek display merge, namely MERGE, is use 14 Mediatek display merge, namely MERGE, is used to merge two slice-per-line
15 inputs into one side-by-side output. 15 inputs into one side-by-side output.
16 MERGE device node must be siblings to the ce 16 MERGE device node must be siblings to the central MMSYS_CONFIG node.
17 For a description of the MMSYS_CONFIG bindin 17 For a description of the MMSYS_CONFIG binding, see
18 Documentation/devicetree/bindings/arm/mediat 18 Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
19 for details. 19 for details.
20 20
21 properties: 21 properties:
22 compatible: 22 compatible:
23 oneOf: 23 oneOf:
24 - enum: 24 - enum:
25 - mediatek,mt8173-disp-merge 25 - mediatek,mt8173-disp-merge
26 - mediatek,mt8195-disp-merge 26 - mediatek,mt8195-disp-merge
27 - mediatek,mt8195-mdp3-merge 27 - mediatek,mt8195-mdp3-merge
28 - items: 28 - items:
29 - const: mediatek,mt6795-disp-merge 29 - const: mediatek,mt6795-disp-merge
30 - const: mediatek,mt8173-disp-merge 30 - const: mediatek,mt8173-disp-merge
31 - items: 31 - items:
32 - const: mediatek,mt8188-disp-merge 32 - const: mediatek,mt8188-disp-merge
33 - const: mediatek,mt8195-disp-merge 33 - const: mediatek,mt8195-disp-merge
34 34
35 reg: 35 reg:
36 maxItems: 1 36 maxItems: 1
37 37
38 interrupts: 38 interrupts:
39 maxItems: 1 39 maxItems: 1
40 40
41 power-domains: 41 power-domains:
42 description: A phandle and PM domain speci 42 description: A phandle and PM domain specifier as defined by bindings of
43 the power controller specified by phandl 43 the power controller specified by phandle. See
44 Documentation/devicetree/bindings/power/ 44 Documentation/devicetree/bindings/power/power-domain.yaml for details.
45 45
46 clocks: 46 clocks:
47 minItems: 1 47 minItems: 1
48 maxItems: 2 48 maxItems: 2
49 49
50 clock-names: 50 clock-names:
51 oneOf: 51 oneOf:
52 - items: 52 - items:
53 - const: merge 53 - const: merge
54 - items: 54 - items:
55 - const: merge 55 - const: merge
56 - const: merge_async 56 - const: merge_async
57 57
58 mediatek,merge-fifo-en: 58 mediatek,merge-fifo-en:
59 description: 59 description:
60 The setting of merge fifo is mainly prov 60 The setting of merge fifo is mainly provided for the display latency
61 buffer to ensure that the back-end panel 61 buffer to ensure that the back-end panel display data will not be
62 underrun, a little more data is needed i 62 underrun, a little more data is needed in the fifo.
63 According to the merge fifo settings, wh 63 According to the merge fifo settings, when the water level is detected
64 to be insufficient, it will trigger RDMA 64 to be insufficient, it will trigger RDMA sending ultra and preulra
65 command to SMI to speed up the data rate 65 command to SMI to speed up the data rate.
66 type: boolean 66 type: boolean
67 67
68 mediatek,merge-mute: 68 mediatek,merge-mute:
69 description: Support mute function. Mute t 69 description: Support mute function. Mute the content of merge output.
70 type: boolean 70 type: boolean
71 71
72 mediatek,gce-client-reg: 72 mediatek,gce-client-reg:
73 description: The register of client driver 73 description: The register of client driver can be configured by gce with
74 4 arguments defined in this property, su 74 4 arguments defined in this property, such as phandle of gce, subsys id,
75 register offset and size. Each GCE subsy 75 register offset and size. Each GCE subsys id is mapping to a client
76 defined in the header include/dt-binding 76 defined in the header include/dt-bindings/gce/<chip>-gce.h.
77 $ref: /schemas/types.yaml#/definitions/pha 77 $ref: /schemas/types.yaml#/definitions/phandle-array
78 maxItems: 1 78 maxItems: 1
79 79
80 resets: 80 resets:
81 description: reset controller 81 description: reset controller
82 See Documentation/devicetree/bindings/re 82 See Documentation/devicetree/bindings/reset/reset.txt for details.
83 maxItems: 1 83 maxItems: 1
84 84
85 required: 85 required:
86 - compatible 86 - compatible
87 - reg 87 - reg
88 - power-domains 88 - power-domains
89 - clocks 89 - clocks
90 90
91 additionalProperties: false 91 additionalProperties: false
92 92
93 examples: 93 examples:
94 - | 94 - |
95 #include <dt-bindings/interrupt-controller 95 #include <dt-bindings/interrupt-controller/arm-gic.h>
96 #include <dt-bindings/clock/mt8173-clk.h> 96 #include <dt-bindings/clock/mt8173-clk.h>
97 #include <dt-bindings/power/mt8173-power.h 97 #include <dt-bindings/power/mt8173-power.h>
98 98
99 soc { 99 soc {
100 #address-cells = <2>; 100 #address-cells = <2>;
101 #size-cells = <2>; 101 #size-cells = <2>;
102 102
103 merge@14017000 { 103 merge@14017000 {
104 compatible = "mediatek,mt8173-disp 104 compatible = "mediatek,mt8173-disp-merge";
105 reg = <0 0x14017000 0 0x1000>; 105 reg = <0 0x14017000 0 0x1000>;
106 power-domains = <&spm MT8173_POWER 106 power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
107 clocks = <&mmsys CLK_MM_DISP_MERGE 107 clocks = <&mmsys CLK_MM_DISP_MERGE>;
108 clock-names = "merge"; 108 clock-names = "merge";
109 }; 109 };
110 }; 110 };
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