1 # SPDX-License-Identifier: (GPL-2.0-only OR BS 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 %YAML 1.2 2 %YAML 1.2
3 --- 3 ---
4 $id: http://devicetree.org/schemas/display/med 4 $id: http://devicetree.org/schemas/display/mediatek/mediatek,padding.yaml#
5 $schema: http://devicetree.org/meta-schemas/co 5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6 6
7 title: MediaTek Display Padding 7 title: MediaTek Display Padding
8 8
9 maintainers: 9 maintainers:
10 - Chun-Kuang Hu <chunkuang.hu@kernel.org> 10 - Chun-Kuang Hu <chunkuang.hu@kernel.org>
11 - Philipp Zabel <p.zabel@pengutronix.de> 11 - Philipp Zabel <p.zabel@pengutronix.de>
12 12
13 description: 13 description:
14 Padding provides ability to add pixels to wi 14 Padding provides ability to add pixels to width and height of a layer with
15 specified colors. Due to hardware design, Mi 15 specified colors. Due to hardware design, Mixer in VDOSYS1 requires
16 width of a layer to be 2-pixel-align, or 4-p 16 width of a layer to be 2-pixel-align, or 4-pixel-align when ETHDR is enabled,
17 we need Padding to deal with odd width. 17 we need Padding to deal with odd width.
18 Please notice that even if the Padding is in 18 Please notice that even if the Padding is in bypass mode, settings in
19 register must be cleared to 0, or undefined 19 register must be cleared to 0, or undefined behaviors could happen.
20 20
21 properties: 21 properties:
22 compatible: 22 compatible:
23 enum: 23 enum:
24 - mediatek,mt8188-disp-padding 24 - mediatek,mt8188-disp-padding
25 - mediatek,mt8195-mdp3-padding 25 - mediatek,mt8195-mdp3-padding
26 26
27 reg: 27 reg:
28 maxItems: 1 28 maxItems: 1
29 29
30 power-domains: 30 power-domains:
31 maxItems: 1 31 maxItems: 1
32 32
33 clocks: 33 clocks:
34 items: 34 items:
35 - description: Padding's clocks 35 - description: Padding's clocks
36 36
37 mediatek,gce-client-reg: 37 mediatek,gce-client-reg:
38 description: 38 description:
39 GCE (Global Command Engine) is a multi-c 39 GCE (Global Command Engine) is a multi-core micro processor that helps
40 its clients to execute commands without 40 its clients to execute commands without interrupting CPU. This property
41 describes GCE client's information that 41 describes GCE client's information that is composed by 4 fields.
42 1. Phandle of the GCE (there may be seve 42 1. Phandle of the GCE (there may be several GCE processors)
43 2. Sub-system ID defined in the dt-bindi 43 2. Sub-system ID defined in the dt-binding like a user ID
44 (Please refer to include/dt-bindings/ 44 (Please refer to include/dt-bindings/gce/<chip>-gce.h)
45 3. Offset from base address of the subsy 45 3. Offset from base address of the subsys you are at
46 4. Size of the register the client needs 46 4. Size of the register the client needs
47 $ref: /schemas/types.yaml#/definitions/pha 47 $ref: /schemas/types.yaml#/definitions/phandle-array
48 items: 48 items:
49 items: 49 items:
50 - description: Phandle of the GCE 50 - description: Phandle of the GCE
51 - description: Subsys ID defined in th 51 - description: Subsys ID defined in the dt-binding
52 - description: Offset from base addres 52 - description: Offset from base address of the subsys
53 - description: Size of register 53 - description: Size of register
54 maxItems: 1 54 maxItems: 1
55 55
56 required: 56 required:
57 - compatible 57 - compatible
58 - reg 58 - reg
59 - power-domains 59 - power-domains
60 - clocks 60 - clocks
61 - mediatek,gce-client-reg 61 - mediatek,gce-client-reg
62 62
63 additionalProperties: false 63 additionalProperties: false
64 64
65 examples: 65 examples:
66 - | 66 - |
67 #include <dt-bindings/interrupt-controller 67 #include <dt-bindings/interrupt-controller/arm-gic.h>
68 #include <dt-bindings/clock/mediatek,mt818 68 #include <dt-bindings/clock/mediatek,mt8188-clk.h>
69 #include <dt-bindings/power/mediatek,mt818 69 #include <dt-bindings/power/mediatek,mt8188-power.h>
70 #include <dt-bindings/gce/mt8195-gce.h> 70 #include <dt-bindings/gce/mt8195-gce.h>
71 71
72 soc { 72 soc {
73 #address-cells = <2>; 73 #address-cells = <2>;
74 #size-cells = <2>; 74 #size-cells = <2>;
75 75
76 padding0: padding@1c11d000 { 76 padding0: padding@1c11d000 {
77 compatible = "mediatek,mt8188-disp 77 compatible = "mediatek,mt8188-disp-padding";
78 reg = <0 0x1c11d000 0 0x1000>; 78 reg = <0 0x1c11d000 0 0x1000>;
79 clocks = <&vdosys1 CLK_VDO1_PADDIN 79 clocks = <&vdosys1 CLK_VDO1_PADDING0>;
80 power-domains = <&spm MT8188_POWER 80 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>;
81 mediatek,gce-client-reg = <&gce0 S 81 mediatek,gce-client-reg = <&gce0 SUBSYS_1c11XXXX 0xd000 0x1000>;
82 }; 82 };
83 }; 83 };
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