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Linux/Documentation/devicetree/bindings/display/mediatek/mediatek,postmask.yaml

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Diff markup

Differences between /Documentation/devicetree/bindings/display/mediatek/mediatek,postmask.yaml (Architecture i386) and /Documentation/devicetree/bindings/display/mediatek/mediatek,postmask.yaml (Architecture m68k)


  1 # SPDX-License-Identifier: (GPL-2.0-only OR BS      1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
  2 %YAML 1.2                                           2 %YAML 1.2
  3 ---                                                 3 ---
  4 $id: http://devicetree.org/schemas/display/med      4 $id: http://devicetree.org/schemas/display/mediatek/mediatek,postmask.yaml#
  5 $schema: http://devicetree.org/meta-schemas/co      5 $schema: http://devicetree.org/meta-schemas/core.yaml#
  6                                                     6 
  7 title: Mediatek display postmask                    7 title: Mediatek display postmask
  8                                                     8 
  9 maintainers:                                        9 maintainers:
 10   - Chun-Kuang Hu <chunkuang.hu@kernel.org>         10   - Chun-Kuang Hu <chunkuang.hu@kernel.org>
 11   - Philipp Zabel <p.zabel@pengutronix.de>          11   - Philipp Zabel <p.zabel@pengutronix.de>
 12                                                    12 
 13 description: |                                     13 description: |
 14   Mediatek display postmask, namely POSTMASK,      14   Mediatek display postmask, namely POSTMASK, provides round corner pattern
 15   generation.                                      15   generation.
 16   POSTMASK device node must be siblings to the     16   POSTMASK device node must be siblings to the central MMSYS_CONFIG node.
 17   For a description of the MMSYS_CONFIG bindin     17   For a description of the MMSYS_CONFIG binding, see
 18   Documentation/devicetree/bindings/arm/mediat     18   Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
 19   for details.                                     19   for details.
 20                                                    20 
 21 properties:                                        21 properties:
 22   compatible:                                      22   compatible:
 23     oneOf:                                         23     oneOf:
 24       - enum:                                      24       - enum:
 25           - mediatek,mt8192-disp-postmask          25           - mediatek,mt8192-disp-postmask
 26       - items:                                     26       - items:
 27           - enum:                                  27           - enum:
 28               - mediatek,mt8186-disp-postmask      28               - mediatek,mt8186-disp-postmask
 29               - mediatek,mt8188-disp-postmask      29               - mediatek,mt8188-disp-postmask
 30           - const: mediatek,mt8192-disp-postma     30           - const: mediatek,mt8192-disp-postmask
 31                                                    31 
 32   reg:                                             32   reg:
 33     maxItems: 1                                    33     maxItems: 1
 34                                                    34 
 35   interrupts:                                      35   interrupts:
 36     maxItems: 1                                    36     maxItems: 1
 37                                                    37 
 38   power-domains:                                   38   power-domains:
 39     description: A phandle and PM domain speci     39     description: A phandle and PM domain specifier as defined by bindings of
 40       the power controller specified by phandl     40       the power controller specified by phandle. See
 41       Documentation/devicetree/bindings/power/     41       Documentation/devicetree/bindings/power/power-domain.yaml for details.
 42                                                    42 
 43   clocks:                                          43   clocks:
 44     items:                                         44     items:
 45       - description: POSTMASK Clock                45       - description: POSTMASK Clock
 46                                                    46 
 47   mediatek,gce-client-reg:                         47   mediatek,gce-client-reg:
 48     description: The register of client driver     48     description: The register of client driver can be configured by gce with
 49       4 arguments defined in this property, su     49       4 arguments defined in this property, such as phandle of gce, subsys id,
 50       register offset and size. Each GCE subsy     50       register offset and size. Each GCE subsys id is mapping to a client
 51       defined in the header include/dt-binding     51       defined in the header include/dt-bindings/gce/<chip>-gce.h.
 52     $ref: /schemas/types.yaml#/definitions/pha     52     $ref: /schemas/types.yaml#/definitions/phandle-array
 53     maxItems: 1                                    53     maxItems: 1
 54                                                    54 
 55 required:                                          55 required:
 56   - compatible                                     56   - compatible
 57   - reg                                            57   - reg
 58   - interrupts                                     58   - interrupts
 59   - power-domains                                  59   - power-domains
 60   - clocks                                         60   - clocks
 61                                                    61 
 62 additionalProperties: false                        62 additionalProperties: false
 63                                                    63 
 64 examples:                                          64 examples:
 65   - |                                              65   - |
 66     #include <dt-bindings/interrupt-controller     66     #include <dt-bindings/interrupt-controller/arm-gic.h>
 67     #include <dt-bindings/clock/mt8192-clk.h>      67     #include <dt-bindings/clock/mt8192-clk.h>
 68     #include <dt-bindings/power/mt8192-power.h     68     #include <dt-bindings/power/mt8192-power.h>
 69     #include <dt-bindings/gce/mt8192-gce.h>        69     #include <dt-bindings/gce/mt8192-gce.h>
 70                                                    70 
 71     soc {                                          71     soc {
 72         #address-cells = <2>;                      72         #address-cells = <2>;
 73         #size-cells = <2>;                         73         #size-cells = <2>;
 74                                                    74 
 75         postmask0: postmask@1400d000 {             75         postmask0: postmask@1400d000 {
 76             compatible = "mediatek,mt8192-disp     76             compatible = "mediatek,mt8192-disp-postmask";
 77             reg = <0 0x1400d000 0 0x1000>;         77             reg = <0 0x1400d000 0 0x1000>;
 78             interrupts = <GIC_SPI 262 IRQ_TYPE     78             interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH 0>;
 79             power-domains = <&scpsys MT8192_PO     79             power-domains = <&scpsys MT8192_POWER_DOMAIN_DISP>;
 80             clocks = <&mmsys CLK_MM_DISP_POSTM     80             clocks = <&mmsys CLK_MM_DISP_POSTMASK0>;
 81             mediatek,gce-client-reg = <&gce SU     81             mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xd000 0x1000>;
 82         };                                         82         };
 83     };                                             83     };
                                                      

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