1 # SPDX-License-Identifier: (GPL-2.0-only OR BS 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 %YAML 1.2 2 %YAML 1.2
3 --- 3 ---
4 $id: http://devicetree.org/schemas/display/msm 4 $id: http://devicetree.org/schemas/display/msm/dp-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/co 5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6 6
7 title: MSM Display Port Controller 7 title: MSM Display Port Controller
8 8
9 maintainers: 9 maintainers:
10 - Kuogee Hsieh <quic_khsieh@quicinc.com> 10 - Kuogee Hsieh <quic_khsieh@quicinc.com>
11 11
12 description: | 12 description: |
13 Device tree bindings for DisplayPort host co 13 Device tree bindings for DisplayPort host controller for MSM targets
14 that are compatible with VESA DisplayPort in 14 that are compatible with VESA DisplayPort interface specification.
15 15
16 properties: 16 properties:
17 compatible: 17 compatible:
18 oneOf: !! 18 enum:
19 - enum: !! 19 - qcom,sc7180-dp
20 - qcom,sc7180-dp !! 20 - qcom,sc7280-dp
21 - qcom,sc7280-dp !! 21 - qcom,sc7280-edp
22 - qcom,sc7280-edp !! 22 - qcom,sc8180x-dp
23 - qcom,sc8180x-dp !! 23 - qcom,sc8180x-edp
24 - qcom,sc8180x-edp !! 24 - qcom,sm8350-dp
25 - qcom,sc8280xp-dp <<
26 - qcom,sc8280xp-edp <<
27 - qcom,sdm845-dp <<
28 - qcom,sm8350-dp <<
29 - qcom,sm8650-dp <<
30 - items: <<
31 - enum: <<
32 - qcom,sm6350-dp <<
33 - qcom,sm8150-dp <<
34 - qcom,sm8250-dp <<
35 - qcom,sm8450-dp <<
36 - qcom,sm8550-dp <<
37 - const: qcom,sm8350-dp <<
38 25
39 reg: 26 reg:
40 minItems: 4 <<
41 items: 27 items:
42 - description: ahb register block 28 - description: ahb register block
43 - description: aux register block 29 - description: aux register block
44 - description: link register block 30 - description: link register block
45 - description: p0 register block 31 - description: p0 register block
46 - description: p1 register block 32 - description: p1 register block
47 33
48 interrupts: 34 interrupts:
49 maxItems: 1 35 maxItems: 1
50 36
51 clocks: 37 clocks:
52 items: 38 items:
53 - description: AHB clock to enable regis 39 - description: AHB clock to enable register access
54 - description: Display Port AUX clock 40 - description: Display Port AUX clock
55 - description: Display Port Link clock 41 - description: Display Port Link clock
56 - description: Link interface clock betw 42 - description: Link interface clock between DP and PHY
57 - description: Display Port Pixel clock 43 - description: Display Port Pixel clock
58 44
59 clock-names: 45 clock-names:
60 items: 46 items:
61 - const: core_iface 47 - const: core_iface
62 - const: core_aux 48 - const: core_aux
63 - const: ctrl_link 49 - const: ctrl_link
64 - const: ctrl_link_iface 50 - const: ctrl_link_iface
65 - const: stream_pixel 51 - const: stream_pixel
66 52
67 assigned-clocks: 53 assigned-clocks:
68 items: 54 items:
69 - description: link clock source 55 - description: link clock source
70 - description: pixel clock source 56 - description: pixel clock source
71 57
72 assigned-clock-parents: 58 assigned-clock-parents:
73 items: 59 items:
74 - description: phy 0 parent 60 - description: phy 0 parent
75 - description: phy 1 parent 61 - description: phy 1 parent
76 62
77 phys: 63 phys:
78 maxItems: 1 64 maxItems: 1
79 65
80 phy-names: 66 phy-names:
81 items: 67 items:
82 - const: dp 68 - const: dp
83 69
84 operating-points-v2: true !! 70 operating-points-v2:
85 !! 71 maxItems: 1
86 opp-table: <<
87 type: object <<
88 72
89 power-domains: 73 power-domains:
90 maxItems: 1 74 maxItems: 1
91 75
92 aux-bus: <<
93 $ref: /schemas/display/dp-aux-bus.yaml# <<
94 <<
95 data-lanes: <<
96 $ref: /schemas/types.yaml#/definitions/uin <<
97 deprecated: true <<
98 minItems: 1 <<
99 maxItems: 4 <<
100 items: <<
101 maximum: 3 <<
102 <<
103 "#sound-dai-cells": 76 "#sound-dai-cells":
104 const: 0 77 const: 0
105 78
106 vdda-0p9-supply: !! 79 vdda-0p9-supply: true
107 deprecated: true !! 80 vdda-1p2-supply: true
108 vdda-1p2-supply: <<
109 deprecated: true <<
110 81
111 ports: 82 ports:
112 $ref: /schemas/graph.yaml#/properties/port 83 $ref: /schemas/graph.yaml#/properties/ports
113 properties: 84 properties:
114 port@0: 85 port@0:
115 $ref: /schemas/graph.yaml#/properties/ 86 $ref: /schemas/graph.yaml#/properties/port
116 description: Input endpoint of the con 87 description: Input endpoint of the controller
117 88
118 port@1: 89 port@1:
119 $ref: /schemas/graph.yaml#/$defs/port- !! 90 $ref: /schemas/graph.yaml#/properties/port
120 unevaluatedProperties: false <<
121 description: Output endpoint of the co 91 description: Output endpoint of the controller
122 properties: <<
123 endpoint: <<
124 $ref: /schemas/media/video-interfa <<
125 unevaluatedProperties: false <<
126 properties: <<
127 data-lanes: <<
128 minItems: 1 <<
129 maxItems: 4 <<
130 items: <<
131 enum: [ 0, 1, 2, 3 ] <<
132 <<
133 link-frequencies: <<
134 minItems: 1 <<
135 maxItems: 4 <<
136 items: <<
137 enum: [ 1620000000, 27000000 <<
138 <<
139 required: <<
140 - port@0 <<
141 - port@1 <<
142 92
143 required: 93 required:
144 - compatible 94 - compatible
145 - reg 95 - reg
146 - interrupts 96 - interrupts
147 - clocks 97 - clocks
148 - clock-names 98 - clock-names
149 - phys 99 - phys
150 - phy-names 100 - phy-names
>> 101 - "#sound-dai-cells"
151 - power-domains 102 - power-domains
152 - ports 103 - ports
153 104
154 allOf: <<
155 # AUX BUS does not exist on DP controllers <<
156 # Audio output also is present only on DP ou <<
157 # p1 regions is present on DP, but not on eD <<
158 - if: <<
159 properties: <<
160 compatible: <<
161 contains: <<
162 enum: <<
163 - qcom,sc7280-edp <<
164 - qcom,sc8180x-edp <<
165 - qcom,sc8280xp-edp <<
166 then: <<
167 properties: <<
168 "#sound-dai-cells": false <<
169 else: <<
170 properties: <<
171 aux-bus: false <<
172 reg: <<
173 minItems: 5 <<
174 required: <<
175 - "#sound-dai-cells" <<
176 <<
177 additionalProperties: false 105 additionalProperties: false
178 106
179 examples: 107 examples:
180 - | 108 - |
181 #include <dt-bindings/interrupt-controller 109 #include <dt-bindings/interrupt-controller/arm-gic.h>
182 #include <dt-bindings/clock/qcom,dispcc-sc 110 #include <dt-bindings/clock/qcom,dispcc-sc7180.h>
183 #include <dt-bindings/power/qcom-rpmpd.h> 111 #include <dt-bindings/power/qcom-rpmpd.h>
184 112
185 displayport-controller@ae90000 { 113 displayport-controller@ae90000 {
186 compatible = "qcom,sc7180-dp"; 114 compatible = "qcom,sc7180-dp";
187 reg = <0xae90000 0x200>, 115 reg = <0xae90000 0x200>,
188 <0xae90200 0x200>, 116 <0xae90200 0x200>,
189 <0xae90400 0xc00>, 117 <0xae90400 0xc00>,
190 <0xae91000 0x400>, 118 <0xae91000 0x400>,
191 <0xae91400 0x400>; 119 <0xae91400 0x400>;
192 interrupt-parent = <&mdss>; 120 interrupt-parent = <&mdss>;
193 interrupts = <12>; 121 interrupts = <12>;
194 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK 122 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
195 <&dispcc DISP_CC_MDSS_DP_AUX_ 123 <&dispcc DISP_CC_MDSS_DP_AUX_CLK>,
196 <&dispcc DISP_CC_MDSS_DP_LINK 124 <&dispcc DISP_CC_MDSS_DP_LINK_CLK>,
197 <&dispcc DISP_CC_MDSS_DP_LINK 125 <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>,
198 <&dispcc DISP_CC_MDSS_DP_PIXE 126 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>;
199 clock-names = "core_iface", "core_aux" 127 clock-names = "core_iface", "core_aux",
200 "ctrl_link", 128 "ctrl_link",
201 "ctrl_link_iface", "stre 129 "ctrl_link_iface", "stream_pixel";
202 130
203 assigned-clocks = <&dispcc DISP_CC_MDS 131 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
204 <&dispcc DISP_CC_MDS 132 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>;
205 133
206 assigned-clock-parents = <&dp_phy 0>, 134 assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>;
207 135
208 phys = <&dp_phy>; 136 phys = <&dp_phy>;
209 phy-names = "dp"; 137 phy-names = "dp";
210 138
211 #sound-dai-cells = <0>; 139 #sound-dai-cells = <0>;
212 140
213 power-domains = <&rpmhpd SC7180_CX>; 141 power-domains = <&rpmhpd SC7180_CX>;
214 142
>> 143 vdda-0p9-supply = <&vdda_usb_ss_dp_core>;
>> 144 vdda-1p2-supply = <&vdda_usb_ss_dp_1p2>;
>> 145
215 ports { 146 ports {
216 #address-cells = <1>; 147 #address-cells = <1>;
217 #size-cells = <0>; 148 #size-cells = <0>;
218 149
219 port@0 { 150 port@0 {
220 reg = <0>; 151 reg = <0>;
221 endpoint { 152 endpoint {
222 remote-endpoint = <&dpu_in 153 remote-endpoint = <&dpu_intf0_out>;
223 }; 154 };
224 }; 155 };
225 156
226 port@1 { 157 port@1 {
227 reg = <1>; 158 reg = <1>;
228 endpoint { 159 endpoint {
229 remote-endpoint = <&typec> 160 remote-endpoint = <&typec>;
230 data-lanes = <0 1>; <<
231 link-frequencies = /bits/ <<
232 }; 161 };
233 }; 162 };
234 }; 163 };
235 }; 164 };
236 ... 165 ...
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