1 # SPDX-License-Identifier: (GPL-2.0-only OR BS 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 %YAML 1.2 2 %YAML 1.2
3 --- 3 ---
4 $id: http://devicetree.org/schemas/display/msm 4 $id: http://devicetree.org/schemas/display/msm/dp-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/co 5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6 6
7 title: MSM Display Port Controller 7 title: MSM Display Port Controller
8 8
9 maintainers: 9 maintainers:
10 - Kuogee Hsieh <quic_khsieh@quicinc.com> 10 - Kuogee Hsieh <quic_khsieh@quicinc.com>
11 11
12 description: | 12 description: |
13 Device tree bindings for DisplayPort host co 13 Device tree bindings for DisplayPort host controller for MSM targets
14 that are compatible with VESA DisplayPort in 14 that are compatible with VESA DisplayPort interface specification.
15 15
16 properties: 16 properties:
17 compatible: 17 compatible:
18 oneOf: !! 18 enum:
19 - enum: !! 19 - qcom,sc7180-dp
20 - qcom,sc7180-dp !! 20 - qcom,sc7280-dp
21 - qcom,sc7280-dp !! 21 - qcom,sc7280-edp
22 - qcom,sc7280-edp !! 22 - qcom,sc8180x-dp
23 - qcom,sc8180x-dp !! 23 - qcom,sc8180x-edp
24 - qcom,sc8180x-edp !! 24 - qcom,sc8280xp-dp
25 - qcom,sc8280xp-dp !! 25 - qcom,sc8280xp-edp
26 - qcom,sc8280xp-edp !! 26 - qcom,sdm845-dp
27 - qcom,sdm845-dp !! 27 - qcom,sm8350-dp
28 - qcom,sm8350-dp <<
29 - qcom,sm8650-dp <<
30 - items: <<
31 - enum: <<
32 - qcom,sm6350-dp <<
33 - qcom,sm8150-dp <<
34 - qcom,sm8250-dp <<
35 - qcom,sm8450-dp <<
36 - qcom,sm8550-dp <<
37 - const: qcom,sm8350-dp <<
38 28
39 reg: 29 reg:
40 minItems: 4 30 minItems: 4
41 items: 31 items:
42 - description: ahb register block 32 - description: ahb register block
43 - description: aux register block 33 - description: aux register block
44 - description: link register block 34 - description: link register block
45 - description: p0 register block 35 - description: p0 register block
46 - description: p1 register block 36 - description: p1 register block
47 37
48 interrupts: 38 interrupts:
49 maxItems: 1 39 maxItems: 1
50 40
51 clocks: 41 clocks:
52 items: 42 items:
53 - description: AHB clock to enable regis 43 - description: AHB clock to enable register access
54 - description: Display Port AUX clock 44 - description: Display Port AUX clock
55 - description: Display Port Link clock 45 - description: Display Port Link clock
56 - description: Link interface clock betw 46 - description: Link interface clock between DP and PHY
57 - description: Display Port Pixel clock 47 - description: Display Port Pixel clock
58 48
59 clock-names: 49 clock-names:
60 items: 50 items:
61 - const: core_iface 51 - const: core_iface
62 - const: core_aux 52 - const: core_aux
63 - const: ctrl_link 53 - const: ctrl_link
64 - const: ctrl_link_iface 54 - const: ctrl_link_iface
65 - const: stream_pixel 55 - const: stream_pixel
66 56
67 assigned-clocks: 57 assigned-clocks:
68 items: 58 items:
69 - description: link clock source 59 - description: link clock source
70 - description: pixel clock source 60 - description: pixel clock source
71 61
72 assigned-clock-parents: 62 assigned-clock-parents:
73 items: 63 items:
74 - description: phy 0 parent 64 - description: phy 0 parent
75 - description: phy 1 parent 65 - description: phy 1 parent
76 66
77 phys: 67 phys:
78 maxItems: 1 68 maxItems: 1
79 69
80 phy-names: 70 phy-names:
81 items: 71 items:
82 - const: dp 72 - const: dp
83 73
84 operating-points-v2: true 74 operating-points-v2: true
85 75
86 opp-table: !! 76 opp-table: true
87 type: object <<
88 77
89 power-domains: 78 power-domains:
90 maxItems: 1 79 maxItems: 1
91 80
92 aux-bus: 81 aux-bus:
93 $ref: /schemas/display/dp-aux-bus.yaml# 82 $ref: /schemas/display/dp-aux-bus.yaml#
94 83
95 data-lanes: 84 data-lanes:
96 $ref: /schemas/types.yaml#/definitions/uin 85 $ref: /schemas/types.yaml#/definitions/uint32-array
97 deprecated: true 86 deprecated: true
98 minItems: 1 87 minItems: 1
99 maxItems: 4 88 maxItems: 4
100 items: 89 items:
101 maximum: 3 90 maximum: 3
102 91
103 "#sound-dai-cells": 92 "#sound-dai-cells":
104 const: 0 93 const: 0
105 94
106 vdda-0p9-supply: 95 vdda-0p9-supply:
107 deprecated: true 96 deprecated: true
108 vdda-1p2-supply: 97 vdda-1p2-supply:
109 deprecated: true 98 deprecated: true
110 99
111 ports: 100 ports:
112 $ref: /schemas/graph.yaml#/properties/port 101 $ref: /schemas/graph.yaml#/properties/ports
113 properties: 102 properties:
114 port@0: 103 port@0:
115 $ref: /schemas/graph.yaml#/properties/ 104 $ref: /schemas/graph.yaml#/properties/port
116 description: Input endpoint of the con 105 description: Input endpoint of the controller
117 106
118 port@1: 107 port@1:
119 $ref: /schemas/graph.yaml#/$defs/port- 108 $ref: /schemas/graph.yaml#/$defs/port-base
120 unevaluatedProperties: false <<
121 description: Output endpoint of the co 109 description: Output endpoint of the controller
122 properties: 110 properties:
123 endpoint: 111 endpoint:
124 $ref: /schemas/media/video-interfa 112 $ref: /schemas/media/video-interfaces.yaml#
125 unevaluatedProperties: false 113 unevaluatedProperties: false
126 properties: 114 properties:
127 data-lanes: 115 data-lanes:
128 minItems: 1 116 minItems: 1
129 maxItems: 4 117 maxItems: 4
130 items: 118 items:
131 enum: [ 0, 1, 2, 3 ] 119 enum: [ 0, 1, 2, 3 ]
132 120
133 link-frequencies: 121 link-frequencies:
134 minItems: 1 122 minItems: 1
135 maxItems: 4 123 maxItems: 4
136 items: 124 items:
137 enum: [ 1620000000, 27000000 125 enum: [ 1620000000, 2700000000, 5400000000, 8100000000 ]
138 126
139 required: 127 required:
140 - port@0 128 - port@0
141 - port@1 129 - port@1
142 130
143 required: 131 required:
144 - compatible 132 - compatible
145 - reg 133 - reg
146 - interrupts 134 - interrupts
147 - clocks 135 - clocks
148 - clock-names 136 - clock-names
149 - phys 137 - phys
150 - phy-names 138 - phy-names
151 - power-domains 139 - power-domains
152 - ports 140 - ports
153 141
154 allOf: 142 allOf:
155 # AUX BUS does not exist on DP controllers 143 # AUX BUS does not exist on DP controllers
156 # Audio output also is present only on DP ou 144 # Audio output also is present only on DP output
157 # p1 regions is present on DP, but not on eD 145 # p1 regions is present on DP, but not on eDP
158 - if: 146 - if:
159 properties: 147 properties:
160 compatible: 148 compatible:
161 contains: 149 contains:
162 enum: 150 enum:
163 - qcom,sc7280-edp 151 - qcom,sc7280-edp
164 - qcom,sc8180x-edp 152 - qcom,sc8180x-edp
165 - qcom,sc8280xp-edp 153 - qcom,sc8280xp-edp
166 then: 154 then:
167 properties: 155 properties:
168 "#sound-dai-cells": false 156 "#sound-dai-cells": false
169 else: 157 else:
170 properties: 158 properties:
171 aux-bus: false 159 aux-bus: false
172 reg: 160 reg:
173 minItems: 5 161 minItems: 5
174 required: 162 required:
175 - "#sound-dai-cells" 163 - "#sound-dai-cells"
176 164
177 additionalProperties: false 165 additionalProperties: false
178 166
179 examples: 167 examples:
180 - | 168 - |
181 #include <dt-bindings/interrupt-controller 169 #include <dt-bindings/interrupt-controller/arm-gic.h>
182 #include <dt-bindings/clock/qcom,dispcc-sc 170 #include <dt-bindings/clock/qcom,dispcc-sc7180.h>
183 #include <dt-bindings/power/qcom-rpmpd.h> 171 #include <dt-bindings/power/qcom-rpmpd.h>
184 172
185 displayport-controller@ae90000 { 173 displayport-controller@ae90000 {
186 compatible = "qcom,sc7180-dp"; 174 compatible = "qcom,sc7180-dp";
187 reg = <0xae90000 0x200>, 175 reg = <0xae90000 0x200>,
188 <0xae90200 0x200>, 176 <0xae90200 0x200>,
189 <0xae90400 0xc00>, 177 <0xae90400 0xc00>,
190 <0xae91000 0x400>, 178 <0xae91000 0x400>,
191 <0xae91400 0x400>; 179 <0xae91400 0x400>;
192 interrupt-parent = <&mdss>; 180 interrupt-parent = <&mdss>;
193 interrupts = <12>; 181 interrupts = <12>;
194 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK 182 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
195 <&dispcc DISP_CC_MDSS_DP_AUX_ 183 <&dispcc DISP_CC_MDSS_DP_AUX_CLK>,
196 <&dispcc DISP_CC_MDSS_DP_LINK 184 <&dispcc DISP_CC_MDSS_DP_LINK_CLK>,
197 <&dispcc DISP_CC_MDSS_DP_LINK 185 <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>,
198 <&dispcc DISP_CC_MDSS_DP_PIXE 186 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>;
199 clock-names = "core_iface", "core_aux" 187 clock-names = "core_iface", "core_aux",
200 "ctrl_link", 188 "ctrl_link",
201 "ctrl_link_iface", "stre 189 "ctrl_link_iface", "stream_pixel";
202 190
203 assigned-clocks = <&dispcc DISP_CC_MDS 191 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
204 <&dispcc DISP_CC_MDS 192 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>;
205 193
206 assigned-clock-parents = <&dp_phy 0>, 194 assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>;
207 195
208 phys = <&dp_phy>; 196 phys = <&dp_phy>;
209 phy-names = "dp"; 197 phy-names = "dp";
210 198
211 #sound-dai-cells = <0>; 199 #sound-dai-cells = <0>;
212 200
213 power-domains = <&rpmhpd SC7180_CX>; 201 power-domains = <&rpmhpd SC7180_CX>;
214 202
215 ports { 203 ports {
216 #address-cells = <1>; 204 #address-cells = <1>;
217 #size-cells = <0>; 205 #size-cells = <0>;
218 206
219 port@0 { 207 port@0 {
220 reg = <0>; 208 reg = <0>;
221 endpoint { 209 endpoint {
222 remote-endpoint = <&dpu_in 210 remote-endpoint = <&dpu_intf0_out>;
223 }; 211 };
224 }; 212 };
225 213
226 port@1 { 214 port@1 {
227 reg = <1>; 215 reg = <1>;
228 endpoint { 216 endpoint {
229 remote-endpoint = <&typec> 217 remote-endpoint = <&typec>;
230 data-lanes = <0 1>; 218 data-lanes = <0 1>;
231 link-frequencies = /bits/ 219 link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>;
232 }; 220 };
233 }; 221 };
234 }; 222 };
235 }; 223 };
236 ... 224 ...
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