1 # SPDX-License-Identifier: (GPL-2.0-only OR BS 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 %YAML 1.2 2 %YAML 1.2
3 --- 3 ---
4 $id: http://devicetree.org/schemas/display/msm 4 $id: http://devicetree.org/schemas/display/msm/dp-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/co 5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6 6
7 title: MSM Display Port Controller 7 title: MSM Display Port Controller
8 8
9 maintainers: 9 maintainers:
10 - Kuogee Hsieh <quic_khsieh@quicinc.com> 10 - Kuogee Hsieh <quic_khsieh@quicinc.com>
11 11
12 description: | 12 description: |
13 Device tree bindings for DisplayPort host co 13 Device tree bindings for DisplayPort host controller for MSM targets
14 that are compatible with VESA DisplayPort in 14 that are compatible with VESA DisplayPort interface specification.
15 15
16 properties: 16 properties:
17 compatible: 17 compatible:
18 oneOf: 18 oneOf:
19 - enum: 19 - enum:
20 - qcom,sc7180-dp 20 - qcom,sc7180-dp
21 - qcom,sc7280-dp 21 - qcom,sc7280-dp
22 - qcom,sc7280-edp 22 - qcom,sc7280-edp
23 - qcom,sc8180x-dp 23 - qcom,sc8180x-dp
24 - qcom,sc8180x-edp 24 - qcom,sc8180x-edp
25 - qcom,sc8280xp-dp 25 - qcom,sc8280xp-dp
26 - qcom,sc8280xp-edp 26 - qcom,sc8280xp-edp
27 - qcom,sdm845-dp 27 - qcom,sdm845-dp
28 - qcom,sm8350-dp 28 - qcom,sm8350-dp
29 - qcom,sm8650-dp <<
30 - items: 29 - items:
31 - enum: 30 - enum:
32 - qcom,sm6350-dp <<
33 - qcom,sm8150-dp <<
34 - qcom,sm8250-dp <<
35 - qcom,sm8450-dp 31 - qcom,sm8450-dp
36 - qcom,sm8550-dp <<
37 - const: qcom,sm8350-dp 32 - const: qcom,sm8350-dp
38 33
39 reg: 34 reg:
40 minItems: 4 35 minItems: 4
41 items: 36 items:
42 - description: ahb register block 37 - description: ahb register block
43 - description: aux register block 38 - description: aux register block
44 - description: link register block 39 - description: link register block
45 - description: p0 register block 40 - description: p0 register block
46 - description: p1 register block 41 - description: p1 register block
47 42
48 interrupts: 43 interrupts:
49 maxItems: 1 44 maxItems: 1
50 45
51 clocks: 46 clocks:
52 items: 47 items:
53 - description: AHB clock to enable regis 48 - description: AHB clock to enable register access
54 - description: Display Port AUX clock 49 - description: Display Port AUX clock
55 - description: Display Port Link clock 50 - description: Display Port Link clock
56 - description: Link interface clock betw 51 - description: Link interface clock between DP and PHY
57 - description: Display Port Pixel clock 52 - description: Display Port Pixel clock
58 53
59 clock-names: 54 clock-names:
60 items: 55 items:
61 - const: core_iface 56 - const: core_iface
62 - const: core_aux 57 - const: core_aux
63 - const: ctrl_link 58 - const: ctrl_link
64 - const: ctrl_link_iface 59 - const: ctrl_link_iface
65 - const: stream_pixel 60 - const: stream_pixel
66 61
67 assigned-clocks: 62 assigned-clocks:
68 items: 63 items:
69 - description: link clock source 64 - description: link clock source
70 - description: pixel clock source 65 - description: pixel clock source
71 66
72 assigned-clock-parents: 67 assigned-clock-parents:
73 items: 68 items:
74 - description: phy 0 parent 69 - description: phy 0 parent
75 - description: phy 1 parent 70 - description: phy 1 parent
76 71
77 phys: 72 phys:
78 maxItems: 1 73 maxItems: 1
79 74
80 phy-names: 75 phy-names:
81 items: 76 items:
82 - const: dp 77 - const: dp
83 78
84 operating-points-v2: true 79 operating-points-v2: true
85 80
86 opp-table: !! 81 opp-table: true
87 type: object <<
88 82
89 power-domains: 83 power-domains:
90 maxItems: 1 84 maxItems: 1
91 85
92 aux-bus: 86 aux-bus:
93 $ref: /schemas/display/dp-aux-bus.yaml# 87 $ref: /schemas/display/dp-aux-bus.yaml#
94 88
95 data-lanes: 89 data-lanes:
96 $ref: /schemas/types.yaml#/definitions/uin 90 $ref: /schemas/types.yaml#/definitions/uint32-array
97 deprecated: true 91 deprecated: true
98 minItems: 1 92 minItems: 1
99 maxItems: 4 93 maxItems: 4
100 items: 94 items:
101 maximum: 3 95 maximum: 3
102 96
103 "#sound-dai-cells": 97 "#sound-dai-cells":
104 const: 0 98 const: 0
105 99
106 vdda-0p9-supply: 100 vdda-0p9-supply:
107 deprecated: true 101 deprecated: true
108 vdda-1p2-supply: 102 vdda-1p2-supply:
109 deprecated: true 103 deprecated: true
110 104
111 ports: 105 ports:
112 $ref: /schemas/graph.yaml#/properties/port 106 $ref: /schemas/graph.yaml#/properties/ports
113 properties: 107 properties:
114 port@0: 108 port@0:
115 $ref: /schemas/graph.yaml#/properties/ 109 $ref: /schemas/graph.yaml#/properties/port
116 description: Input endpoint of the con 110 description: Input endpoint of the controller
117 111
118 port@1: 112 port@1:
119 $ref: /schemas/graph.yaml#/$defs/port- 113 $ref: /schemas/graph.yaml#/$defs/port-base
120 unevaluatedProperties: false <<
121 description: Output endpoint of the co 114 description: Output endpoint of the controller
122 properties: 115 properties:
123 endpoint: 116 endpoint:
124 $ref: /schemas/media/video-interfa 117 $ref: /schemas/media/video-interfaces.yaml#
125 unevaluatedProperties: false 118 unevaluatedProperties: false
126 properties: 119 properties:
127 data-lanes: 120 data-lanes:
128 minItems: 1 121 minItems: 1
129 maxItems: 4 122 maxItems: 4
130 items: 123 items:
131 enum: [ 0, 1, 2, 3 ] 124 enum: [ 0, 1, 2, 3 ]
132 125
133 link-frequencies: 126 link-frequencies:
134 minItems: 1 127 minItems: 1
135 maxItems: 4 128 maxItems: 4
136 items: 129 items:
137 enum: [ 1620000000, 27000000 130 enum: [ 1620000000, 2700000000, 5400000000, 8100000000 ]
138 131
139 required: 132 required:
140 - port@0 133 - port@0
141 - port@1 134 - port@1
142 135
143 required: 136 required:
144 - compatible 137 - compatible
145 - reg 138 - reg
146 - interrupts 139 - interrupts
147 - clocks 140 - clocks
148 - clock-names 141 - clock-names
149 - phys 142 - phys
150 - phy-names 143 - phy-names
151 - power-domains 144 - power-domains
152 - ports 145 - ports
153 146
154 allOf: 147 allOf:
155 # AUX BUS does not exist on DP controllers 148 # AUX BUS does not exist on DP controllers
156 # Audio output also is present only on DP ou 149 # Audio output also is present only on DP output
157 # p1 regions is present on DP, but not on eD 150 # p1 regions is present on DP, but not on eDP
158 - if: 151 - if:
159 properties: 152 properties:
160 compatible: 153 compatible:
161 contains: 154 contains:
162 enum: 155 enum:
163 - qcom,sc7280-edp 156 - qcom,sc7280-edp
164 - qcom,sc8180x-edp 157 - qcom,sc8180x-edp
165 - qcom,sc8280xp-edp 158 - qcom,sc8280xp-edp
166 then: 159 then:
167 properties: 160 properties:
168 "#sound-dai-cells": false 161 "#sound-dai-cells": false
169 else: 162 else:
170 properties: 163 properties:
171 aux-bus: false 164 aux-bus: false
172 reg: 165 reg:
173 minItems: 5 166 minItems: 5
174 required: 167 required:
175 - "#sound-dai-cells" 168 - "#sound-dai-cells"
176 169
177 additionalProperties: false 170 additionalProperties: false
178 171
179 examples: 172 examples:
180 - | 173 - |
181 #include <dt-bindings/interrupt-controller 174 #include <dt-bindings/interrupt-controller/arm-gic.h>
182 #include <dt-bindings/clock/qcom,dispcc-sc 175 #include <dt-bindings/clock/qcom,dispcc-sc7180.h>
183 #include <dt-bindings/power/qcom-rpmpd.h> 176 #include <dt-bindings/power/qcom-rpmpd.h>
184 177
185 displayport-controller@ae90000 { 178 displayport-controller@ae90000 {
186 compatible = "qcom,sc7180-dp"; 179 compatible = "qcom,sc7180-dp";
187 reg = <0xae90000 0x200>, 180 reg = <0xae90000 0x200>,
188 <0xae90200 0x200>, 181 <0xae90200 0x200>,
189 <0xae90400 0xc00>, 182 <0xae90400 0xc00>,
190 <0xae91000 0x400>, 183 <0xae91000 0x400>,
191 <0xae91400 0x400>; 184 <0xae91400 0x400>;
192 interrupt-parent = <&mdss>; 185 interrupt-parent = <&mdss>;
193 interrupts = <12>; 186 interrupts = <12>;
194 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK 187 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
195 <&dispcc DISP_CC_MDSS_DP_AUX_ 188 <&dispcc DISP_CC_MDSS_DP_AUX_CLK>,
196 <&dispcc DISP_CC_MDSS_DP_LINK 189 <&dispcc DISP_CC_MDSS_DP_LINK_CLK>,
197 <&dispcc DISP_CC_MDSS_DP_LINK 190 <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>,
198 <&dispcc DISP_CC_MDSS_DP_PIXE 191 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>;
199 clock-names = "core_iface", "core_aux" 192 clock-names = "core_iface", "core_aux",
200 "ctrl_link", 193 "ctrl_link",
201 "ctrl_link_iface", "stre 194 "ctrl_link_iface", "stream_pixel";
202 195
203 assigned-clocks = <&dispcc DISP_CC_MDS 196 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
204 <&dispcc DISP_CC_MDS 197 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>;
205 198
206 assigned-clock-parents = <&dp_phy 0>, 199 assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>;
207 200
208 phys = <&dp_phy>; 201 phys = <&dp_phy>;
209 phy-names = "dp"; 202 phy-names = "dp";
210 203
211 #sound-dai-cells = <0>; 204 #sound-dai-cells = <0>;
212 205
213 power-domains = <&rpmhpd SC7180_CX>; 206 power-domains = <&rpmhpd SC7180_CX>;
214 207
215 ports { 208 ports {
216 #address-cells = <1>; 209 #address-cells = <1>;
217 #size-cells = <0>; 210 #size-cells = <0>;
218 211
219 port@0 { 212 port@0 {
220 reg = <0>; 213 reg = <0>;
221 endpoint { 214 endpoint {
222 remote-endpoint = <&dpu_in 215 remote-endpoint = <&dpu_intf0_out>;
223 }; 216 };
224 }; 217 };
225 218
226 port@1 { 219 port@1 {
227 reg = <1>; 220 reg = <1>;
228 endpoint { 221 endpoint {
229 remote-endpoint = <&typec> 222 remote-endpoint = <&typec>;
230 data-lanes = <0 1>; 223 data-lanes = <0 1>;
231 link-frequencies = /bits/ 224 link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>;
232 }; 225 };
233 }; 226 };
234 }; 227 };
235 }; 228 };
236 ... 229 ...
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