1 # SPDX-License-Identifier: (GPL-2.0-only OR BS 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 %YAML 1.2 2 %YAML 1.2
3 --- 3 ---
4 $id: http://devicetree.org/schemas/display/msm 4 $id: http://devicetree.org/schemas/display/msm/dp-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/co 5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6 6
7 title: MSM Display Port Controller 7 title: MSM Display Port Controller
8 8
9 maintainers: 9 maintainers:
10 - Kuogee Hsieh <quic_khsieh@quicinc.com> 10 - Kuogee Hsieh <quic_khsieh@quicinc.com>
11 11
12 description: | 12 description: |
13 Device tree bindings for DisplayPort host co 13 Device tree bindings for DisplayPort host controller for MSM targets
14 that are compatible with VESA DisplayPort in 14 that are compatible with VESA DisplayPort interface specification.
15 15
16 properties: 16 properties:
17 compatible: 17 compatible:
18 oneOf: 18 oneOf:
19 - enum: 19 - enum:
20 - qcom,sc7180-dp 20 - qcom,sc7180-dp
21 - qcom,sc7280-dp 21 - qcom,sc7280-dp
22 - qcom,sc7280-edp 22 - qcom,sc7280-edp
23 - qcom,sc8180x-dp 23 - qcom,sc8180x-dp
24 - qcom,sc8180x-edp 24 - qcom,sc8180x-edp
25 - qcom,sc8280xp-dp 25 - qcom,sc8280xp-dp
26 - qcom,sc8280xp-edp 26 - qcom,sc8280xp-edp
27 - qcom,sdm845-dp 27 - qcom,sdm845-dp
28 - qcom,sm8350-dp 28 - qcom,sm8350-dp
29 - qcom,sm8650-dp <<
30 - items: 29 - items:
31 - enum: 30 - enum:
32 - qcom,sm6350-dp <<
33 - qcom,sm8150-dp <<
34 - qcom,sm8250-dp <<
35 - qcom,sm8450-dp 31 - qcom,sm8450-dp
36 - qcom,sm8550-dp 32 - qcom,sm8550-dp
37 - const: qcom,sm8350-dp 33 - const: qcom,sm8350-dp
38 34
39 reg: 35 reg:
40 minItems: 4 36 minItems: 4
41 items: 37 items:
42 - description: ahb register block 38 - description: ahb register block
43 - description: aux register block 39 - description: aux register block
44 - description: link register block 40 - description: link register block
45 - description: p0 register block 41 - description: p0 register block
46 - description: p1 register block 42 - description: p1 register block
47 43
48 interrupts: 44 interrupts:
49 maxItems: 1 45 maxItems: 1
50 46
51 clocks: 47 clocks:
52 items: 48 items:
53 - description: AHB clock to enable regis 49 - description: AHB clock to enable register access
54 - description: Display Port AUX clock 50 - description: Display Port AUX clock
55 - description: Display Port Link clock 51 - description: Display Port Link clock
56 - description: Link interface clock betw 52 - description: Link interface clock between DP and PHY
57 - description: Display Port Pixel clock 53 - description: Display Port Pixel clock
58 54
59 clock-names: 55 clock-names:
60 items: 56 items:
61 - const: core_iface 57 - const: core_iface
62 - const: core_aux 58 - const: core_aux
63 - const: ctrl_link 59 - const: ctrl_link
64 - const: ctrl_link_iface 60 - const: ctrl_link_iface
65 - const: stream_pixel 61 - const: stream_pixel
66 62
67 assigned-clocks: 63 assigned-clocks:
68 items: 64 items:
69 - description: link clock source 65 - description: link clock source
70 - description: pixel clock source 66 - description: pixel clock source
71 67
72 assigned-clock-parents: 68 assigned-clock-parents:
73 items: 69 items:
74 - description: phy 0 parent 70 - description: phy 0 parent
75 - description: phy 1 parent 71 - description: phy 1 parent
76 72
77 phys: 73 phys:
78 maxItems: 1 74 maxItems: 1
79 75
80 phy-names: 76 phy-names:
81 items: 77 items:
82 - const: dp 78 - const: dp
83 79
84 operating-points-v2: true 80 operating-points-v2: true
85 81
86 opp-table: !! 82 opp-table: true
87 type: object <<
88 83
89 power-domains: 84 power-domains:
90 maxItems: 1 85 maxItems: 1
91 86
92 aux-bus: 87 aux-bus:
93 $ref: /schemas/display/dp-aux-bus.yaml# 88 $ref: /schemas/display/dp-aux-bus.yaml#
94 89
95 data-lanes: 90 data-lanes:
96 $ref: /schemas/types.yaml#/definitions/uin 91 $ref: /schemas/types.yaml#/definitions/uint32-array
97 deprecated: true 92 deprecated: true
98 minItems: 1 93 minItems: 1
99 maxItems: 4 94 maxItems: 4
100 items: 95 items:
101 maximum: 3 96 maximum: 3
102 97
103 "#sound-dai-cells": 98 "#sound-dai-cells":
104 const: 0 99 const: 0
105 100
106 vdda-0p9-supply: 101 vdda-0p9-supply:
107 deprecated: true 102 deprecated: true
108 vdda-1p2-supply: 103 vdda-1p2-supply:
109 deprecated: true 104 deprecated: true
110 105
111 ports: 106 ports:
112 $ref: /schemas/graph.yaml#/properties/port 107 $ref: /schemas/graph.yaml#/properties/ports
113 properties: 108 properties:
114 port@0: 109 port@0:
115 $ref: /schemas/graph.yaml#/properties/ 110 $ref: /schemas/graph.yaml#/properties/port
116 description: Input endpoint of the con 111 description: Input endpoint of the controller
117 112
118 port@1: 113 port@1:
119 $ref: /schemas/graph.yaml#/$defs/port- 114 $ref: /schemas/graph.yaml#/$defs/port-base
120 unevaluatedProperties: false <<
121 description: Output endpoint of the co 115 description: Output endpoint of the controller
122 properties: 116 properties:
123 endpoint: 117 endpoint:
124 $ref: /schemas/media/video-interfa 118 $ref: /schemas/media/video-interfaces.yaml#
125 unevaluatedProperties: false 119 unevaluatedProperties: false
126 properties: 120 properties:
127 data-lanes: 121 data-lanes:
128 minItems: 1 122 minItems: 1
129 maxItems: 4 123 maxItems: 4
130 items: 124 items:
131 enum: [ 0, 1, 2, 3 ] 125 enum: [ 0, 1, 2, 3 ]
132 126
133 link-frequencies: 127 link-frequencies:
134 minItems: 1 128 minItems: 1
135 maxItems: 4 129 maxItems: 4
136 items: 130 items:
137 enum: [ 1620000000, 27000000 131 enum: [ 1620000000, 2700000000, 5400000000, 8100000000 ]
138 132
139 required: 133 required:
140 - port@0 134 - port@0
141 - port@1 135 - port@1
142 136
143 required: 137 required:
144 - compatible 138 - compatible
145 - reg 139 - reg
146 - interrupts 140 - interrupts
147 - clocks 141 - clocks
148 - clock-names 142 - clock-names
149 - phys 143 - phys
150 - phy-names 144 - phy-names
151 - power-domains 145 - power-domains
152 - ports 146 - ports
153 147
154 allOf: 148 allOf:
155 # AUX BUS does not exist on DP controllers 149 # AUX BUS does not exist on DP controllers
156 # Audio output also is present only on DP ou 150 # Audio output also is present only on DP output
157 # p1 regions is present on DP, but not on eD 151 # p1 regions is present on DP, but not on eDP
158 - if: 152 - if:
159 properties: 153 properties:
160 compatible: 154 compatible:
161 contains: 155 contains:
162 enum: 156 enum:
163 - qcom,sc7280-edp 157 - qcom,sc7280-edp
164 - qcom,sc8180x-edp 158 - qcom,sc8180x-edp
165 - qcom,sc8280xp-edp 159 - qcom,sc8280xp-edp
166 then: 160 then:
167 properties: 161 properties:
168 "#sound-dai-cells": false 162 "#sound-dai-cells": false
169 else: 163 else:
170 properties: 164 properties:
171 aux-bus: false 165 aux-bus: false
172 reg: 166 reg:
173 minItems: 5 167 minItems: 5
174 required: 168 required:
175 - "#sound-dai-cells" 169 - "#sound-dai-cells"
176 170
177 additionalProperties: false 171 additionalProperties: false
178 172
179 examples: 173 examples:
180 - | 174 - |
181 #include <dt-bindings/interrupt-controller 175 #include <dt-bindings/interrupt-controller/arm-gic.h>
182 #include <dt-bindings/clock/qcom,dispcc-sc 176 #include <dt-bindings/clock/qcom,dispcc-sc7180.h>
183 #include <dt-bindings/power/qcom-rpmpd.h> 177 #include <dt-bindings/power/qcom-rpmpd.h>
184 178
185 displayport-controller@ae90000 { 179 displayport-controller@ae90000 {
186 compatible = "qcom,sc7180-dp"; 180 compatible = "qcom,sc7180-dp";
187 reg = <0xae90000 0x200>, 181 reg = <0xae90000 0x200>,
188 <0xae90200 0x200>, 182 <0xae90200 0x200>,
189 <0xae90400 0xc00>, 183 <0xae90400 0xc00>,
190 <0xae91000 0x400>, 184 <0xae91000 0x400>,
191 <0xae91400 0x400>; 185 <0xae91400 0x400>;
192 interrupt-parent = <&mdss>; 186 interrupt-parent = <&mdss>;
193 interrupts = <12>; 187 interrupts = <12>;
194 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK 188 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
195 <&dispcc DISP_CC_MDSS_DP_AUX_ 189 <&dispcc DISP_CC_MDSS_DP_AUX_CLK>,
196 <&dispcc DISP_CC_MDSS_DP_LINK 190 <&dispcc DISP_CC_MDSS_DP_LINK_CLK>,
197 <&dispcc DISP_CC_MDSS_DP_LINK 191 <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>,
198 <&dispcc DISP_CC_MDSS_DP_PIXE 192 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>;
199 clock-names = "core_iface", "core_aux" 193 clock-names = "core_iface", "core_aux",
200 "ctrl_link", 194 "ctrl_link",
201 "ctrl_link_iface", "stre 195 "ctrl_link_iface", "stream_pixel";
202 196
203 assigned-clocks = <&dispcc DISP_CC_MDS 197 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
204 <&dispcc DISP_CC_MDS 198 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>;
205 199
206 assigned-clock-parents = <&dp_phy 0>, 200 assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>;
207 201
208 phys = <&dp_phy>; 202 phys = <&dp_phy>;
209 phy-names = "dp"; 203 phy-names = "dp";
210 204
211 #sound-dai-cells = <0>; 205 #sound-dai-cells = <0>;
212 206
213 power-domains = <&rpmhpd SC7180_CX>; 207 power-domains = <&rpmhpd SC7180_CX>;
214 208
215 ports { 209 ports {
216 #address-cells = <1>; 210 #address-cells = <1>;
217 #size-cells = <0>; 211 #size-cells = <0>;
218 212
219 port@0 { 213 port@0 {
220 reg = <0>; 214 reg = <0>;
221 endpoint { 215 endpoint {
222 remote-endpoint = <&dpu_in 216 remote-endpoint = <&dpu_intf0_out>;
223 }; 217 };
224 }; 218 };
225 219
226 port@1 { 220 port@1 {
227 reg = <1>; 221 reg = <1>;
228 endpoint { 222 endpoint {
229 remote-endpoint = <&typec> 223 remote-endpoint = <&typec>;
230 data-lanes = <0 1>; 224 data-lanes = <0 1>;
231 link-frequencies = /bits/ 225 link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>;
232 }; 226 };
233 }; 227 };
234 }; 228 };
235 }; 229 };
236 ... 230 ...
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