1 # SPDX-License-Identifier: (GPL-2.0-only OR BS 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 %YAML 1.2 2 %YAML 1.2
3 --- 3 ---
4 $id: http://devicetree.org/schemas/display/msm 4 $id: http://devicetree.org/schemas/display/msm/dp-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/co 5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6 6
7 title: MSM Display Port Controller 7 title: MSM Display Port Controller
8 8
9 maintainers: 9 maintainers:
10 - Kuogee Hsieh <quic_khsieh@quicinc.com> 10 - Kuogee Hsieh <quic_khsieh@quicinc.com>
11 11
12 description: | 12 description: |
13 Device tree bindings for DisplayPort host co 13 Device tree bindings for DisplayPort host controller for MSM targets
14 that are compatible with VESA DisplayPort in 14 that are compatible with VESA DisplayPort interface specification.
15 15
16 properties: 16 properties:
17 compatible: 17 compatible:
18 oneOf: 18 oneOf:
19 - enum: 19 - enum:
20 - qcom,sc7180-dp 20 - qcom,sc7180-dp
21 - qcom,sc7280-dp 21 - qcom,sc7280-dp
22 - qcom,sc7280-edp 22 - qcom,sc7280-edp
23 - qcom,sc8180x-dp 23 - qcom,sc8180x-dp
24 - qcom,sc8180x-edp 24 - qcom,sc8180x-edp
25 - qcom,sc8280xp-dp 25 - qcom,sc8280xp-dp
26 - qcom,sc8280xp-edp 26 - qcom,sc8280xp-edp
27 - qcom,sdm845-dp 27 - qcom,sdm845-dp
28 - qcom,sm8350-dp 28 - qcom,sm8350-dp
29 - qcom,sm8650-dp <<
30 - items: 29 - items:
31 - enum: 30 - enum:
32 - qcom,sm6350-dp <<
33 - qcom,sm8150-dp <<
34 - qcom,sm8250-dp 31 - qcom,sm8250-dp
35 - qcom,sm8450-dp 32 - qcom,sm8450-dp
36 - qcom,sm8550-dp 33 - qcom,sm8550-dp
37 - const: qcom,sm8350-dp 34 - const: qcom,sm8350-dp
38 35
39 reg: 36 reg:
40 minItems: 4 37 minItems: 4
41 items: 38 items:
42 - description: ahb register block 39 - description: ahb register block
43 - description: aux register block 40 - description: aux register block
44 - description: link register block 41 - description: link register block
45 - description: p0 register block 42 - description: p0 register block
46 - description: p1 register block 43 - description: p1 register block
47 44
48 interrupts: 45 interrupts:
49 maxItems: 1 46 maxItems: 1
50 47
51 clocks: 48 clocks:
52 items: 49 items:
53 - description: AHB clock to enable regis 50 - description: AHB clock to enable register access
54 - description: Display Port AUX clock 51 - description: Display Port AUX clock
55 - description: Display Port Link clock 52 - description: Display Port Link clock
56 - description: Link interface clock betw 53 - description: Link interface clock between DP and PHY
57 - description: Display Port Pixel clock 54 - description: Display Port Pixel clock
58 55
59 clock-names: 56 clock-names:
60 items: 57 items:
61 - const: core_iface 58 - const: core_iface
62 - const: core_aux 59 - const: core_aux
63 - const: ctrl_link 60 - const: ctrl_link
64 - const: ctrl_link_iface 61 - const: ctrl_link_iface
65 - const: stream_pixel 62 - const: stream_pixel
66 63
67 assigned-clocks: 64 assigned-clocks:
68 items: 65 items:
69 - description: link clock source 66 - description: link clock source
70 - description: pixel clock source 67 - description: pixel clock source
71 68
72 assigned-clock-parents: 69 assigned-clock-parents:
73 items: 70 items:
74 - description: phy 0 parent 71 - description: phy 0 parent
75 - description: phy 1 parent 72 - description: phy 1 parent
76 73
77 phys: 74 phys:
78 maxItems: 1 75 maxItems: 1
79 76
80 phy-names: 77 phy-names:
81 items: 78 items:
82 - const: dp 79 - const: dp
83 80
84 operating-points-v2: true 81 operating-points-v2: true
85 82
86 opp-table: 83 opp-table:
87 type: object 84 type: object
88 85
89 power-domains: 86 power-domains:
90 maxItems: 1 87 maxItems: 1
91 88
92 aux-bus: 89 aux-bus:
93 $ref: /schemas/display/dp-aux-bus.yaml# 90 $ref: /schemas/display/dp-aux-bus.yaml#
94 91
95 data-lanes: 92 data-lanes:
96 $ref: /schemas/types.yaml#/definitions/uin 93 $ref: /schemas/types.yaml#/definitions/uint32-array
97 deprecated: true 94 deprecated: true
98 minItems: 1 95 minItems: 1
99 maxItems: 4 96 maxItems: 4
100 items: 97 items:
101 maximum: 3 98 maximum: 3
102 99
103 "#sound-dai-cells": 100 "#sound-dai-cells":
104 const: 0 101 const: 0
105 102
106 vdda-0p9-supply: 103 vdda-0p9-supply:
107 deprecated: true 104 deprecated: true
108 vdda-1p2-supply: 105 vdda-1p2-supply:
109 deprecated: true 106 deprecated: true
110 107
111 ports: 108 ports:
112 $ref: /schemas/graph.yaml#/properties/port 109 $ref: /schemas/graph.yaml#/properties/ports
113 properties: 110 properties:
114 port@0: 111 port@0:
115 $ref: /schemas/graph.yaml#/properties/ 112 $ref: /schemas/graph.yaml#/properties/port
116 description: Input endpoint of the con 113 description: Input endpoint of the controller
117 114
118 port@1: 115 port@1:
119 $ref: /schemas/graph.yaml#/$defs/port- 116 $ref: /schemas/graph.yaml#/$defs/port-base
120 unevaluatedProperties: false 117 unevaluatedProperties: false
121 description: Output endpoint of the co 118 description: Output endpoint of the controller
122 properties: 119 properties:
123 endpoint: 120 endpoint:
124 $ref: /schemas/media/video-interfa 121 $ref: /schemas/media/video-interfaces.yaml#
125 unevaluatedProperties: false 122 unevaluatedProperties: false
126 properties: 123 properties:
127 data-lanes: 124 data-lanes:
128 minItems: 1 125 minItems: 1
129 maxItems: 4 126 maxItems: 4
130 items: 127 items:
131 enum: [ 0, 1, 2, 3 ] 128 enum: [ 0, 1, 2, 3 ]
132 129
133 link-frequencies: 130 link-frequencies:
134 minItems: 1 131 minItems: 1
135 maxItems: 4 132 maxItems: 4
136 items: 133 items:
137 enum: [ 1620000000, 27000000 134 enum: [ 1620000000, 2700000000, 5400000000, 8100000000 ]
138 135
139 required: 136 required:
140 - port@0 137 - port@0
141 - port@1 138 - port@1
142 139
143 required: 140 required:
144 - compatible 141 - compatible
145 - reg 142 - reg
146 - interrupts 143 - interrupts
147 - clocks 144 - clocks
148 - clock-names 145 - clock-names
149 - phys 146 - phys
150 - phy-names 147 - phy-names
151 - power-domains 148 - power-domains
152 - ports 149 - ports
153 150
154 allOf: 151 allOf:
155 # AUX BUS does not exist on DP controllers 152 # AUX BUS does not exist on DP controllers
156 # Audio output also is present only on DP ou 153 # Audio output also is present only on DP output
157 # p1 regions is present on DP, but not on eD 154 # p1 regions is present on DP, but not on eDP
158 - if: 155 - if:
159 properties: 156 properties:
160 compatible: 157 compatible:
161 contains: 158 contains:
162 enum: 159 enum:
163 - qcom,sc7280-edp 160 - qcom,sc7280-edp
164 - qcom,sc8180x-edp 161 - qcom,sc8180x-edp
165 - qcom,sc8280xp-edp 162 - qcom,sc8280xp-edp
166 then: 163 then:
167 properties: 164 properties:
168 "#sound-dai-cells": false 165 "#sound-dai-cells": false
169 else: 166 else:
170 properties: 167 properties:
171 aux-bus: false 168 aux-bus: false
172 reg: 169 reg:
173 minItems: 5 170 minItems: 5
174 required: 171 required:
175 - "#sound-dai-cells" 172 - "#sound-dai-cells"
176 173
177 additionalProperties: false 174 additionalProperties: false
178 175
179 examples: 176 examples:
180 - | 177 - |
181 #include <dt-bindings/interrupt-controller 178 #include <dt-bindings/interrupt-controller/arm-gic.h>
182 #include <dt-bindings/clock/qcom,dispcc-sc 179 #include <dt-bindings/clock/qcom,dispcc-sc7180.h>
183 #include <dt-bindings/power/qcom-rpmpd.h> 180 #include <dt-bindings/power/qcom-rpmpd.h>
184 181
185 displayport-controller@ae90000 { 182 displayport-controller@ae90000 {
186 compatible = "qcom,sc7180-dp"; 183 compatible = "qcom,sc7180-dp";
187 reg = <0xae90000 0x200>, 184 reg = <0xae90000 0x200>,
188 <0xae90200 0x200>, 185 <0xae90200 0x200>,
189 <0xae90400 0xc00>, 186 <0xae90400 0xc00>,
190 <0xae91000 0x400>, 187 <0xae91000 0x400>,
191 <0xae91400 0x400>; 188 <0xae91400 0x400>;
192 interrupt-parent = <&mdss>; 189 interrupt-parent = <&mdss>;
193 interrupts = <12>; 190 interrupts = <12>;
194 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK 191 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
195 <&dispcc DISP_CC_MDSS_DP_AUX_ 192 <&dispcc DISP_CC_MDSS_DP_AUX_CLK>,
196 <&dispcc DISP_CC_MDSS_DP_LINK 193 <&dispcc DISP_CC_MDSS_DP_LINK_CLK>,
197 <&dispcc DISP_CC_MDSS_DP_LINK 194 <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>,
198 <&dispcc DISP_CC_MDSS_DP_PIXE 195 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>;
199 clock-names = "core_iface", "core_aux" 196 clock-names = "core_iface", "core_aux",
200 "ctrl_link", 197 "ctrl_link",
201 "ctrl_link_iface", "stre 198 "ctrl_link_iface", "stream_pixel";
202 199
203 assigned-clocks = <&dispcc DISP_CC_MDS 200 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
204 <&dispcc DISP_CC_MDS 201 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>;
205 202
206 assigned-clock-parents = <&dp_phy 0>, 203 assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>;
207 204
208 phys = <&dp_phy>; 205 phys = <&dp_phy>;
209 phy-names = "dp"; 206 phy-names = "dp";
210 207
211 #sound-dai-cells = <0>; 208 #sound-dai-cells = <0>;
212 209
213 power-domains = <&rpmhpd SC7180_CX>; 210 power-domains = <&rpmhpd SC7180_CX>;
214 211
215 ports { 212 ports {
216 #address-cells = <1>; 213 #address-cells = <1>;
217 #size-cells = <0>; 214 #size-cells = <0>;
218 215
219 port@0 { 216 port@0 {
220 reg = <0>; 217 reg = <0>;
221 endpoint { 218 endpoint {
222 remote-endpoint = <&dpu_in 219 remote-endpoint = <&dpu_intf0_out>;
223 }; 220 };
224 }; 221 };
225 222
226 port@1 { 223 port@1 {
227 reg = <1>; 224 reg = <1>;
228 endpoint { 225 endpoint {
229 remote-endpoint = <&typec> 226 remote-endpoint = <&typec>;
230 data-lanes = <0 1>; 227 data-lanes = <0 1>;
231 link-frequencies = /bits/ 228 link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>;
232 }; 229 };
233 }; 230 };
234 }; 231 };
235 }; 232 };
236 ... 233 ...
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