1 # SPDX-License-Identifier: (GPL-2.0-only OR BS 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 %YAML 1.2 2 %YAML 1.2
3 --- 3 ---
4 $id: http://devicetree.org/schemas/display/msm 4 $id: http://devicetree.org/schemas/display/msm/dp-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/co 5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6 6
7 title: MSM Display Port Controller 7 title: MSM Display Port Controller
8 8
9 maintainers: 9 maintainers:
10 - Kuogee Hsieh <quic_khsieh@quicinc.com> 10 - Kuogee Hsieh <quic_khsieh@quicinc.com>
11 11
12 description: | 12 description: |
13 Device tree bindings for DisplayPort host co 13 Device tree bindings for DisplayPort host controller for MSM targets
14 that are compatible with VESA DisplayPort in 14 that are compatible with VESA DisplayPort interface specification.
15 15
16 properties: 16 properties:
17 compatible: 17 compatible:
18 oneOf: 18 oneOf:
19 - enum: 19 - enum:
20 - qcom,sc7180-dp 20 - qcom,sc7180-dp
21 - qcom,sc7280-dp 21 - qcom,sc7280-dp
22 - qcom,sc7280-edp 22 - qcom,sc7280-edp
23 - qcom,sc8180x-dp 23 - qcom,sc8180x-dp
24 - qcom,sc8180x-edp 24 - qcom,sc8180x-edp
25 - qcom,sc8280xp-dp 25 - qcom,sc8280xp-dp
26 - qcom,sc8280xp-edp 26 - qcom,sc8280xp-edp
27 - qcom,sdm845-dp 27 - qcom,sdm845-dp
28 - qcom,sm8350-dp 28 - qcom,sm8350-dp
29 - qcom,sm8650-dp 29 - qcom,sm8650-dp
30 - items: 30 - items:
31 - enum: 31 - enum:
32 - qcom,sm6350-dp <<
33 - qcom,sm8150-dp 32 - qcom,sm8150-dp
34 - qcom,sm8250-dp 33 - qcom,sm8250-dp
35 - qcom,sm8450-dp 34 - qcom,sm8450-dp
36 - qcom,sm8550-dp 35 - qcom,sm8550-dp
37 - const: qcom,sm8350-dp 36 - const: qcom,sm8350-dp
38 37
39 reg: 38 reg:
40 minItems: 4 39 minItems: 4
41 items: 40 items:
42 - description: ahb register block 41 - description: ahb register block
43 - description: aux register block 42 - description: aux register block
44 - description: link register block 43 - description: link register block
45 - description: p0 register block 44 - description: p0 register block
46 - description: p1 register block 45 - description: p1 register block
47 46
48 interrupts: 47 interrupts:
49 maxItems: 1 48 maxItems: 1
50 49
51 clocks: 50 clocks:
52 items: 51 items:
53 - description: AHB clock to enable regis 52 - description: AHB clock to enable register access
54 - description: Display Port AUX clock 53 - description: Display Port AUX clock
55 - description: Display Port Link clock 54 - description: Display Port Link clock
56 - description: Link interface clock betw 55 - description: Link interface clock between DP and PHY
57 - description: Display Port Pixel clock 56 - description: Display Port Pixel clock
58 57
59 clock-names: 58 clock-names:
60 items: 59 items:
61 - const: core_iface 60 - const: core_iface
62 - const: core_aux 61 - const: core_aux
63 - const: ctrl_link 62 - const: ctrl_link
64 - const: ctrl_link_iface 63 - const: ctrl_link_iface
65 - const: stream_pixel 64 - const: stream_pixel
66 65
67 assigned-clocks: 66 assigned-clocks:
68 items: 67 items:
69 - description: link clock source 68 - description: link clock source
70 - description: pixel clock source 69 - description: pixel clock source
71 70
72 assigned-clock-parents: 71 assigned-clock-parents:
73 items: 72 items:
74 - description: phy 0 parent 73 - description: phy 0 parent
75 - description: phy 1 parent 74 - description: phy 1 parent
76 75
77 phys: 76 phys:
78 maxItems: 1 77 maxItems: 1
79 78
80 phy-names: 79 phy-names:
81 items: 80 items:
82 - const: dp 81 - const: dp
83 82
84 operating-points-v2: true 83 operating-points-v2: true
85 84
86 opp-table: 85 opp-table:
87 type: object 86 type: object
88 87
89 power-domains: 88 power-domains:
90 maxItems: 1 89 maxItems: 1
91 90
92 aux-bus: 91 aux-bus:
93 $ref: /schemas/display/dp-aux-bus.yaml# 92 $ref: /schemas/display/dp-aux-bus.yaml#
94 93
95 data-lanes: 94 data-lanes:
96 $ref: /schemas/types.yaml#/definitions/uin 95 $ref: /schemas/types.yaml#/definitions/uint32-array
97 deprecated: true 96 deprecated: true
98 minItems: 1 97 minItems: 1
99 maxItems: 4 98 maxItems: 4
100 items: 99 items:
101 maximum: 3 100 maximum: 3
102 101
103 "#sound-dai-cells": 102 "#sound-dai-cells":
104 const: 0 103 const: 0
105 104
106 vdda-0p9-supply: 105 vdda-0p9-supply:
107 deprecated: true 106 deprecated: true
108 vdda-1p2-supply: 107 vdda-1p2-supply:
109 deprecated: true 108 deprecated: true
110 109
111 ports: 110 ports:
112 $ref: /schemas/graph.yaml#/properties/port 111 $ref: /schemas/graph.yaml#/properties/ports
113 properties: 112 properties:
114 port@0: 113 port@0:
115 $ref: /schemas/graph.yaml#/properties/ 114 $ref: /schemas/graph.yaml#/properties/port
116 description: Input endpoint of the con 115 description: Input endpoint of the controller
117 116
118 port@1: 117 port@1:
119 $ref: /schemas/graph.yaml#/$defs/port- 118 $ref: /schemas/graph.yaml#/$defs/port-base
120 unevaluatedProperties: false 119 unevaluatedProperties: false
121 description: Output endpoint of the co 120 description: Output endpoint of the controller
122 properties: 121 properties:
123 endpoint: 122 endpoint:
124 $ref: /schemas/media/video-interfa 123 $ref: /schemas/media/video-interfaces.yaml#
125 unevaluatedProperties: false 124 unevaluatedProperties: false
126 properties: 125 properties:
127 data-lanes: 126 data-lanes:
128 minItems: 1 127 minItems: 1
129 maxItems: 4 128 maxItems: 4
130 items: 129 items:
131 enum: [ 0, 1, 2, 3 ] 130 enum: [ 0, 1, 2, 3 ]
132 131
133 link-frequencies: 132 link-frequencies:
134 minItems: 1 133 minItems: 1
135 maxItems: 4 134 maxItems: 4
136 items: 135 items:
137 enum: [ 1620000000, 27000000 136 enum: [ 1620000000, 2700000000, 5400000000, 8100000000 ]
138 137
139 required: 138 required:
140 - port@0 139 - port@0
141 - port@1 140 - port@1
142 141
143 required: 142 required:
144 - compatible 143 - compatible
145 - reg 144 - reg
146 - interrupts 145 - interrupts
147 - clocks 146 - clocks
148 - clock-names 147 - clock-names
149 - phys 148 - phys
150 - phy-names 149 - phy-names
151 - power-domains 150 - power-domains
152 - ports 151 - ports
153 152
154 allOf: 153 allOf:
155 # AUX BUS does not exist on DP controllers 154 # AUX BUS does not exist on DP controllers
156 # Audio output also is present only on DP ou 155 # Audio output also is present only on DP output
157 # p1 regions is present on DP, but not on eD 156 # p1 regions is present on DP, but not on eDP
158 - if: 157 - if:
159 properties: 158 properties:
160 compatible: 159 compatible:
161 contains: 160 contains:
162 enum: 161 enum:
163 - qcom,sc7280-edp 162 - qcom,sc7280-edp
164 - qcom,sc8180x-edp 163 - qcom,sc8180x-edp
165 - qcom,sc8280xp-edp 164 - qcom,sc8280xp-edp
166 then: 165 then:
167 properties: 166 properties:
168 "#sound-dai-cells": false 167 "#sound-dai-cells": false
169 else: 168 else:
170 properties: 169 properties:
171 aux-bus: false 170 aux-bus: false
172 reg: 171 reg:
173 minItems: 5 172 minItems: 5
174 required: 173 required:
175 - "#sound-dai-cells" 174 - "#sound-dai-cells"
176 175
177 additionalProperties: false 176 additionalProperties: false
178 177
179 examples: 178 examples:
180 - | 179 - |
181 #include <dt-bindings/interrupt-controller 180 #include <dt-bindings/interrupt-controller/arm-gic.h>
182 #include <dt-bindings/clock/qcom,dispcc-sc 181 #include <dt-bindings/clock/qcom,dispcc-sc7180.h>
183 #include <dt-bindings/power/qcom-rpmpd.h> 182 #include <dt-bindings/power/qcom-rpmpd.h>
184 183
185 displayport-controller@ae90000 { 184 displayport-controller@ae90000 {
186 compatible = "qcom,sc7180-dp"; 185 compatible = "qcom,sc7180-dp";
187 reg = <0xae90000 0x200>, 186 reg = <0xae90000 0x200>,
188 <0xae90200 0x200>, 187 <0xae90200 0x200>,
189 <0xae90400 0xc00>, 188 <0xae90400 0xc00>,
190 <0xae91000 0x400>, 189 <0xae91000 0x400>,
191 <0xae91400 0x400>; 190 <0xae91400 0x400>;
192 interrupt-parent = <&mdss>; 191 interrupt-parent = <&mdss>;
193 interrupts = <12>; 192 interrupts = <12>;
194 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK 193 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
195 <&dispcc DISP_CC_MDSS_DP_AUX_ 194 <&dispcc DISP_CC_MDSS_DP_AUX_CLK>,
196 <&dispcc DISP_CC_MDSS_DP_LINK 195 <&dispcc DISP_CC_MDSS_DP_LINK_CLK>,
197 <&dispcc DISP_CC_MDSS_DP_LINK 196 <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>,
198 <&dispcc DISP_CC_MDSS_DP_PIXE 197 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>;
199 clock-names = "core_iface", "core_aux" 198 clock-names = "core_iface", "core_aux",
200 "ctrl_link", 199 "ctrl_link",
201 "ctrl_link_iface", "stre 200 "ctrl_link_iface", "stream_pixel";
202 201
203 assigned-clocks = <&dispcc DISP_CC_MDS 202 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
204 <&dispcc DISP_CC_MDS 203 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>;
205 204
206 assigned-clock-parents = <&dp_phy 0>, 205 assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>;
207 206
208 phys = <&dp_phy>; 207 phys = <&dp_phy>;
209 phy-names = "dp"; 208 phy-names = "dp";
210 209
211 #sound-dai-cells = <0>; 210 #sound-dai-cells = <0>;
212 211
213 power-domains = <&rpmhpd SC7180_CX>; 212 power-domains = <&rpmhpd SC7180_CX>;
214 213
215 ports { 214 ports {
216 #address-cells = <1>; 215 #address-cells = <1>;
217 #size-cells = <0>; 216 #size-cells = <0>;
218 217
219 port@0 { 218 port@0 {
220 reg = <0>; 219 reg = <0>;
221 endpoint { 220 endpoint {
222 remote-endpoint = <&dpu_in 221 remote-endpoint = <&dpu_intf0_out>;
223 }; 222 };
224 }; 223 };
225 224
226 port@1 { 225 port@1 {
227 reg = <1>; 226 reg = <1>;
228 endpoint { 227 endpoint {
229 remote-endpoint = <&typec> 228 remote-endpoint = <&typec>;
230 data-lanes = <0 1>; 229 data-lanes = <0 1>;
231 link-frequencies = /bits/ 230 link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>;
232 }; 231 };
233 }; 232 };
234 }; 233 };
235 }; 234 };
236 ... 235 ...
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