1 # SPDX-License-Identifier: GPL-2.0-only OR BSD !! 1 # SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause 2 %YAML 1.2 2 %YAML 1.2 3 --- 3 --- 4 $id: http://devicetree.org/schemas/display/msm 4 $id: http://devicetree.org/schemas/display/msm/dsi-controller-main.yaml# 5 $schema: http://devicetree.org/meta-schemas/co 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 6 6 7 title: Qualcomm Display DSI controller 7 title: Qualcomm Display DSI controller 8 8 9 maintainers: 9 maintainers: 10 - Krishna Manikandan <quic_mkrishn@quicinc.co 10 - Krishna Manikandan <quic_mkrishn@quicinc.com> 11 11 >> 12 allOf: >> 13 - $ref: "../dsi-controller.yaml#" >> 14 12 properties: 15 properties: 13 compatible: 16 compatible: 14 oneOf: !! 17 enum: 15 - items: !! 18 - qcom,mdss-dsi-ctrl 16 - enum: !! 19 - qcom,dsi-ctrl-6g-qcm2290 17 - qcom,apq8064-dsi-ctrl << 18 - qcom,msm8226-dsi-ctrl << 19 - qcom,msm8916-dsi-ctrl << 20 - qcom,msm8953-dsi-ctrl << 21 - qcom,msm8974-dsi-ctrl << 22 - qcom,msm8976-dsi-ctrl << 23 - qcom,msm8996-dsi-ctrl << 24 - qcom,msm8998-dsi-ctrl << 25 - qcom,qcm2290-dsi-ctrl << 26 - qcom,sc7180-dsi-ctrl << 27 - qcom,sc7280-dsi-ctrl << 28 - qcom,sdm660-dsi-ctrl << 29 - qcom,sdm670-dsi-ctrl << 30 - qcom,sdm845-dsi-ctrl << 31 - qcom,sm6115-dsi-ctrl << 32 - qcom,sm6125-dsi-ctrl << 33 - qcom,sm6350-dsi-ctrl << 34 - qcom,sm6375-dsi-ctrl << 35 - qcom,sm7150-dsi-ctrl << 36 - qcom,sm8150-dsi-ctrl << 37 - qcom,sm8250-dsi-ctrl << 38 - qcom,sm8350-dsi-ctrl << 39 - qcom,sm8450-dsi-ctrl << 40 - qcom,sm8550-dsi-ctrl << 41 - qcom,sm8650-dsi-ctrl << 42 - const: qcom,mdss-dsi-ctrl << 43 - enum: << 44 - qcom,dsi-ctrl-6g-qcm2290 << 45 - qcom,mdss-dsi-ctrl # This should a << 46 deprecated: true << 47 20 48 reg: 21 reg: 49 maxItems: 1 22 maxItems: 1 50 23 51 reg-names: 24 reg-names: 52 const: dsi_ctrl 25 const: dsi_ctrl 53 26 54 interrupts: 27 interrupts: 55 maxItems: 1 28 maxItems: 1 56 29 57 clocks: 30 clocks: 58 description: | !! 31 items: 59 Several clocks are used, depending on th !! 32 - description: Display byte clock 60 - bus:: Display AHB clock. !! 33 - description: Display byte interface clock 61 - byte:: Display byte clock. !! 34 - description: Display pixel clock 62 - byte_intf:: Display byte interface cl !! 35 - description: Display core clock 63 - core:: Display core clock. !! 36 - description: Display AHB clock 64 - core_mss:: Core MultiMedia SubSystem !! 37 - description: Display AXI clock 65 - iface:: Display AXI clock. << 66 - mdp_core:: MDP Core clock. << 67 - mnoc:: MNOC clock << 68 - pixel:: Display pixel clock. << 69 minItems: 3 << 70 maxItems: 9 << 71 38 72 clock-names: 39 clock-names: 73 minItems: 3 !! 40 items: 74 maxItems: 9 !! 41 - const: byte >> 42 - const: byte_intf >> 43 - const: pixel >> 44 - const: core >> 45 - const: iface >> 46 - const: bus 75 47 76 phys: 48 phys: 77 maxItems: 1 49 maxItems: 1 78 50 79 phy-names: 51 phy-names: 80 deprecated: true 52 deprecated: true 81 const: dsi 53 const: dsi 82 54 >> 55 "#address-cells": true >> 56 >> 57 "#size-cells": true >> 58 83 syscon-sfpb: 59 syscon-sfpb: 84 description: A phandle to mmss_sfpb syscon 60 description: A phandle to mmss_sfpb syscon node (only for DSIv2). 85 $ref: /schemas/types.yaml#/definitions/pha !! 61 $ref: "/schemas/types.yaml#/definitions/phandle" 86 62 87 qcom,dual-dsi-mode: 63 qcom,dual-dsi-mode: 88 type: boolean 64 type: boolean 89 description: | 65 description: | 90 Indicates if the DSI controller is drivi 66 Indicates if the DSI controller is driving a panel which needs 91 2 DSI links. 67 2 DSI links. 92 68 93 qcom,master-dsi: << 94 type: boolean << 95 description: | << 96 Indicates if the DSI controller is the m << 97 qcom,dual-dsi-mode enabled. << 98 << 99 qcom,sync-dual-dsi: << 100 type: boolean << 101 description: | << 102 Indicates if the DSI controller needs to << 103 with MIPI DCS commands when qcom,dual-ds << 104 << 105 assigned-clocks: 69 assigned-clocks: 106 minItems: 2 !! 70 maxItems: 2 107 maxItems: 4 << 108 description: | 71 description: | 109 Parents of "byte" and "pixel" for the gi 72 Parents of "byte" and "pixel" for the given platform. 110 For DSIv2 platforms this should contain << 111 "pixel_src" clocks. << 112 73 113 assigned-clock-parents: 74 assigned-clock-parents: 114 minItems: 2 !! 75 maxItems: 2 115 maxItems: 4 << 116 description: | 76 description: | 117 The Byte clock and Pixel clock PLL outpu 77 The Byte clock and Pixel clock PLL outputs provided by a DSI PHY block. 118 78 119 power-domains: 79 power-domains: 120 maxItems: 1 80 maxItems: 1 121 81 122 operating-points-v2: true 82 operating-points-v2: true 123 83 124 opp-table: 84 opp-table: 125 type: object 85 type: object 126 86 127 ports: 87 ports: 128 $ref: /schemas/graph.yaml#/properties/port !! 88 $ref: "/schemas/graph.yaml#/properties/ports" 129 description: | 89 description: | 130 Contains DSI controller input and output 90 Contains DSI controller input and output ports as children, each 131 containing one endpoint subnode. 91 containing one endpoint subnode. 132 92 133 properties: 93 properties: 134 port@0: 94 port@0: 135 $ref: /schemas/graph.yaml#/$defs/port- !! 95 $ref: "/schemas/graph.yaml#/$defs/port-base" 136 unevaluatedProperties: false 96 unevaluatedProperties: false 137 description: | 97 description: | 138 Input endpoints of the controller. 98 Input endpoints of the controller. 139 properties: 99 properties: 140 endpoint: 100 endpoint: 141 $ref: /schemas/media/video-interfa 101 $ref: /schemas/media/video-interfaces.yaml# 142 unevaluatedProperties: false 102 unevaluatedProperties: false 143 properties: 103 properties: 144 data-lanes: 104 data-lanes: 145 maxItems: 4 105 maxItems: 4 146 minItems: 1 !! 106 minItems: 4 147 items: 107 items: 148 enum: [ 0, 1, 2, 3 ] 108 enum: [ 0, 1, 2, 3 ] 149 109 150 port@1: 110 port@1: 151 $ref: /schemas/graph.yaml#/$defs/port- !! 111 $ref: "/schemas/graph.yaml#/$defs/port-base" 152 unevaluatedProperties: false 112 unevaluatedProperties: false 153 description: | 113 description: | 154 Output endpoints of the controller. 114 Output endpoints of the controller. 155 properties: 115 properties: 156 endpoint: 116 endpoint: 157 $ref: /schemas/media/video-interfa 117 $ref: /schemas/media/video-interfaces.yaml# 158 unevaluatedProperties: false 118 unevaluatedProperties: false 159 properties: 119 properties: 160 data-lanes: 120 data-lanes: 161 maxItems: 4 121 maxItems: 4 162 minItems: 1 !! 122 minItems: 4 163 items: 123 items: 164 enum: [ 0, 1, 2, 3 ] 124 enum: [ 0, 1, 2, 3 ] 165 125 166 qcom,te-source: << 167 $ref: /schemas/types.yaml#/def << 168 description: << 169 Specifies the source of vsyn << 170 tearing elimination. << 171 default: mdp_vsync_p << 172 enum: << 173 - mdp_vsync_p << 174 - mdp_vsync_s << 175 - mdp_vsync_e << 176 - timer0 << 177 - timer1 << 178 - timer2 << 179 - timer3 << 180 - timer4 << 181 << 182 required: 126 required: 183 - port@0 127 - port@0 184 - port@1 128 - port@1 185 129 186 avdd-supply: << 187 description: << 188 Phandle to vdd regulator device node << 189 << 190 refgen-supply: << 191 description: << 192 Phandle to REFGEN regulator device node << 193 << 194 vcca-supply: << 195 description: << 196 Phandle to vdd regulator device node << 197 << 198 vdd-supply: << 199 description: << 200 VDD regulator << 201 << 202 vddio-supply: << 203 description: << 204 VDD-IO regulator << 205 << 206 vdda-supply: << 207 description: << 208 VDDA regulator << 209 << 210 required: 130 required: 211 - compatible 131 - compatible 212 - reg 132 - reg 213 - reg-names 133 - reg-names 214 - interrupts 134 - interrupts 215 - clocks 135 - clocks 216 - clock-names 136 - clock-names 217 - phys 137 - phys 218 - assigned-clocks 138 - assigned-clocks 219 - assigned-clock-parents 139 - assigned-clock-parents 220 - ports 140 - ports 221 141 222 allOf: !! 142 additionalProperties: false 223 - $ref: ../dsi-controller.yaml# << 224 - if: << 225 properties: << 226 compatible: << 227 contains: << 228 enum: << 229 - qcom,apq8064-dsi-ctrl << 230 then: << 231 properties: << 232 clocks: << 233 maxItems: 7 << 234 clock-names: << 235 items: << 236 - const: iface << 237 - const: bus << 238 - const: core_mmss << 239 - const: src << 240 - const: byte << 241 - const: pixel << 242 - const: core << 243 << 244 - if: << 245 properties: << 246 compatible: << 247 contains: << 248 enum: << 249 - qcom,msm8916-dsi-ctrl << 250 then: << 251 properties: << 252 clocks: << 253 maxItems: 6 << 254 clock-names: << 255 items: << 256 - const: mdp_core << 257 - const: iface << 258 - const: bus << 259 - const: byte << 260 - const: pixel << 261 - const: core << 262 << 263 - if: << 264 properties: << 265 compatible: << 266 contains: << 267 enum: << 268 - qcom,msm8953-dsi-ctrl << 269 - qcom,msm8976-dsi-ctrl << 270 then: << 271 properties: << 272 clocks: << 273 maxItems: 6 << 274 clock-names: << 275 items: << 276 - const: mdp_core << 277 - const: iface << 278 - const: bus << 279 - const: byte << 280 - const: pixel << 281 - const: core << 282 << 283 - if: << 284 properties: << 285 compatible: << 286 contains: << 287 enum: << 288 - qcom,msm8226-dsi-ctrl << 289 - qcom,msm8974-dsi-ctrl << 290 then: << 291 properties: << 292 clocks: << 293 maxItems: 7 << 294 clock-names: << 295 items: << 296 - const: mdp_core << 297 - const: iface << 298 - const: bus << 299 - const: byte << 300 - const: pixel << 301 - const: core << 302 - const: core_mmss << 303 << 304 - if: << 305 properties: << 306 compatible: << 307 contains: << 308 enum: << 309 - qcom,msm8996-dsi-ctrl << 310 then: << 311 properties: << 312 clocks: << 313 maxItems: 7 << 314 clock-names: << 315 items: << 316 - const: mdp_core << 317 - const: byte << 318 - const: iface << 319 - const: bus << 320 - const: core_mmss << 321 - const: pixel << 322 - const: core << 323 << 324 - if: << 325 properties: << 326 compatible: << 327 contains: << 328 enum: << 329 - qcom,msm8998-dsi-ctrl << 330 - qcom,sm6125-dsi-ctrl << 331 - qcom,sm6350-dsi-ctrl << 332 then: << 333 properties: << 334 clocks: << 335 maxItems: 6 << 336 clock-names: << 337 items: << 338 - const: byte << 339 - const: byte_intf << 340 - const: pixel << 341 - const: core << 342 - const: iface << 343 - const: bus << 344 << 345 - if: << 346 properties: << 347 compatible: << 348 contains: << 349 enum: << 350 - qcom,sc7180-dsi-ctrl << 351 - qcom,sc7280-dsi-ctrl << 352 - qcom,sm7150-dsi-ctrl << 353 - qcom,sm8150-dsi-ctrl << 354 - qcom,sm8250-dsi-ctrl << 355 - qcom,sm8350-dsi-ctrl << 356 - qcom,sm8450-dsi-ctrl << 357 - qcom,sm8550-dsi-ctrl << 358 - qcom,sm8650-dsi-ctrl << 359 then: << 360 properties: << 361 clocks: << 362 maxItems: 6 << 363 clock-names: << 364 items: << 365 - const: byte << 366 - const: byte_intf << 367 - const: pixel << 368 - const: core << 369 - const: iface << 370 - const: bus << 371 << 372 - if: << 373 properties: << 374 compatible: << 375 contains: << 376 enum: << 377 - qcom,sdm660-dsi-ctrl << 378 then: << 379 properties: << 380 clocks: << 381 maxItems: 9 << 382 clock-names: << 383 items: << 384 - const: mdp_core << 385 - const: byte << 386 - const: byte_intf << 387 - const: mnoc << 388 - const: iface << 389 - const: bus << 390 - const: core_mmss << 391 - const: pixel << 392 - const: core << 393 << 394 - if: << 395 properties: << 396 compatible: << 397 contains: << 398 enum: << 399 - qcom,sdm845-dsi-ctrl << 400 - qcom,sm6115-dsi-ctrl << 401 - qcom,sm6375-dsi-ctrl << 402 then: << 403 properties: << 404 clocks: << 405 maxItems: 6 << 406 clock-names: << 407 items: << 408 - const: byte << 409 - const: byte_intf << 410 - const: pixel << 411 - const: core << 412 - const: iface << 413 - const: bus << 414 << 415 unevaluatedProperties: false << 416 143 417 examples: 144 examples: 418 - | 145 - | 419 #include <dt-bindings/interrupt-controlle 146 #include <dt-bindings/interrupt-controller/arm-gic.h> 420 #include <dt-bindings/clock/qcom,dispcc-s 147 #include <dt-bindings/clock/qcom,dispcc-sdm845.h> 421 #include <dt-bindings/clock/qcom,gcc-sdm8 148 #include <dt-bindings/clock/qcom,gcc-sdm845.h> 422 #include <dt-bindings/power/qcom-rpmpd.h> 149 #include <dt-bindings/power/qcom-rpmpd.h> 423 150 424 dsi@ae94000 { 151 dsi@ae94000 { 425 compatible = "qcom,sc7180-dsi-ctrl" !! 152 compatible = "qcom,mdss-dsi-ctrl"; 426 reg = <0x0ae94000 0x400>; 153 reg = <0x0ae94000 0x400>; 427 reg-names = "dsi_ctrl"; 154 reg-names = "dsi_ctrl"; 428 155 429 #address-cells = <1>; 156 #address-cells = <1>; 430 #size-cells = <0>; 157 #size-cells = <0>; 431 158 432 interrupt-parent = <&mdss>; 159 interrupt-parent = <&mdss>; 433 interrupts = <4>; 160 interrupts = <4>; 434 161 435 clocks = <&dispcc DISP_CC_MDSS_BYTE 162 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 436 <&dispcc DISP_CC_MDSS_BYTE 163 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 437 <&dispcc DISP_CC_MDSS_PCLK 164 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 438 <&dispcc DISP_CC_MDSS_ESC0 165 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 439 <&dispcc DISP_CC_MDSS_AHB_ 166 <&dispcc DISP_CC_MDSS_AHB_CLK>, 440 <&dispcc DISP_CC_MDSS_AXI_ 167 <&dispcc DISP_CC_MDSS_AXI_CLK>; 441 clock-names = "byte", 168 clock-names = "byte", 442 "byte_intf", 169 "byte_intf", 443 "pixel", 170 "pixel", 444 "core", 171 "core", 445 "iface", 172 "iface", 446 "bus"; 173 "bus"; 447 174 448 phys = <&dsi0_phy>; 175 phys = <&dsi0_phy>; 449 phy-names = "dsi"; 176 phy-names = "dsi"; 450 177 451 assigned-clocks = <&dispcc DISP_CC_ 178 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; 452 assigned-clock-parents = <&dsi_phy 179 assigned-clock-parents = <&dsi_phy 0>, <&dsi_phy 1>; 453 180 454 power-domains = <&rpmhpd SC7180_CX> 181 power-domains = <&rpmhpd SC7180_CX>; 455 operating-points-v2 = <&dsi_opp_tab 182 operating-points-v2 = <&dsi_opp_table>; 456 183 457 ports { 184 ports { 458 #address-cells = <1>; 185 #address-cells = <1>; 459 #size-cells = <0>; 186 #size-cells = <0>; 460 187 461 port@0 { 188 port@0 { 462 reg = <0>; 189 reg = <0>; 463 dsi0_in: endpoint { 190 dsi0_in: endpoint { 464 remote-endp 191 remote-endpoint = <&dpu_intf1_out>; 465 }; 192 }; 466 }; 193 }; 467 194 468 port@1 { 195 port@1 { 469 reg = <1>; 196 reg = <1>; 470 dsi0_out: endpoint { 197 dsi0_out: endpoint { 471 remote-endp 198 remote-endpoint = <&sn65dsi86_in>; 472 data-lanes 199 data-lanes = <0 1 2 3>; 473 qcom,te-sou << 474 }; 200 }; 475 }; 201 }; 476 }; 202 }; 477 }; 203 }; 478 ... 204 ...
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